Manual megaAVR 0-series - ATmega3208/3209/4808/4809 microcontrollers (Microchip)

megaAVR® 0-Series Manual Introduction
The ATmega3208/3209/4808/4809 microcontrollers of the megaAVR® 0-series are using the AVR® processor with hardware multiplier, running at up to 20 MHz, with a wide range of Flash sizes up to 48 KB, up to 6 KB of SRAM, and 256 bytes of EEPROM in 28-, 32-, or 48-pin package. The series uses the latest technologies from Microchip with a flexible and low-power architecture including Event System and SleepWalking, accurate analog features and advanced peripherals. This Manual contains the general descriptions of the peripherals. While the available peripherals have identical features and show the same behavior across the series, packages with fewer pins support a subset of signals. Refer to the Data Sheet of the individual device for available pins and signals.
Features
• AVR® CPU – Single-cycle I/O access – Two-level interrupt controller – Two-cycle hardware multiplier • Memories – Up to 48 KB In-system self-programmable Flash memory – 256B EEPROM – Up to 6 KB SRAM – Write/Erase endurance: • Flash 10,000 cycles • EEPROM 100,000 cycles – Data retention: 20 Years at 85°C • System – Power-on Reset (POR) circuit – Brown-out Detection (BOD) – Clock options: • Lockable 20 MHz low power internal oscillator • 32.768 kHz Ultra Low-Power (ULP) internal oscillator • 32.768 kHz external crystal oscillator • External clock input – Single-pin Unified Program Debug Interface (UPDI) – Three sleep modes: • Idle with all peripherals running and mode for immediate wake-up time © 2018 Microchip Technology Inc.
Datasheet Preliminary
DS40002015A-page 1 Document Outline Introduction Features Table of Contents 1. Block Diagram 2. megaAVR® 0-series Overview 2.1. Memory Overview 2.2. Peripheral Overview 3. Conventions 3.1. Numerical Notation 3.2. Memory Size and Type 3.3. Frequency and Time 3.4. Registers and Bits 3.4.1. Addressing Registers from Header Files 4. Acronyms and Abbreviations 5. Memories 5.1. Overview 5.2. Memory Map 5.3. In-System Reprogrammable Flash Program Memory 5.4. SRAM Data Memory 5.5. EEPROM Data Memory 5.6. User Row (USERROW) 5.7. Signature Row (SIGROW) 5.7.1. Signature Row Summary - SIGROW 5.7.2. Signature Row Description 5.7.2.1. Device ID n 5.7.2.2. Serial Number Byte n 5.7.2.3. Temperature Sensor Calibration n 5.7.2.4. OSC16 Error at 3V 5.7.2.5. OSC16 Error at 5V 5.7.2.6. OSC20 Error at 3V 5.7.2.7. OSC20 Error at 5V 5.8. Fuses (FUSE) 5.8.1. Fuse Summary - FUSE 5.8.2. Fuse Description 5.8.2.1. Watchdog Configuration 5.8.2.2. BOD Configuration 5.8.2.3. Oscillator Configuration 5.8.2.4. System Configuration 0 5.8.2.5. System Configuration 1 5.8.2.6. Application Code End 5.8.2.7. Boot End 5.8.2.8. Lockbits 5.9. Memory Section Access from CPU and UPDI on Locked Device 5.10. I/O Memory 5.10.1. Register Summary - GPIOR 5.10.2. Register Description - GPIOR 5.10.2.1. General Purpose I/O Register n 6. Peripherals and Architecture 6.1. Peripheral Module Address Map 6.2. Interrupt Vector Mapping 6.3. System Configuration (SYSCFG) 6.3.1. Register Summary - SYSCFG 6.3.2. Register Description - SYSCFG 6.3.2.1. Device Revision ID Register 7. AVR CPU 7.1. Features 7.2. Overview 7.3. Architecture 7.4. Arithmetic Logic Unit (ALU) 7.4.1. Hardware Multiplier 7.5. Functional Description 7.5.1. Program Flow 7.5.2. Instruction Execution Timing 7.5.3. Status Register 7.5.4. Stack and Stack Pointer 7.5.5. Register File 7.5.5.1. The X-, Y-, and Z-Registers 7.5.6. Accessing 16-Bit Registers 7.5.7. Configuration Change Protection (CCP) 7.5.7.1. Sequence for Write Operation to Configuration Change Protected I/O Registers 7.5.7.2. Sequence for Execution of Self-Programming 7.6. Register Summary - CPU 7.7. Register Description 7.7.1. Configuration Change Protection 7.7.2. Stack Pointer 7.7.3. Status Register 8. Nonvolatile Memory Controller (NVMCTRL) 8.1. Features 8.2. Overview 8.2.1. Block Diagram 8.3. Functional Description 8.3.1. Memory Organization 8.3.1.1. Flash 8.3.1.2. EEPROM 8.3.1.3. User Row 8.3.2. Memory Access 8.3.2.1. Read 8.3.2.2. Page Buffer Load 8.3.2.3. Programming 8.3.2.4. Commands 8.3.2.4.1. Write Command 8.3.2.4.2. Erase Command 8.3.2.4.3. Erase-Write Operation 8.3.2.4.4. Page Buffer Clear Command 8.3.2.4.5. Chip Erase Command 8.3.2.4.6. EEPROM Erase Command 8.3.2.4.7. Fuse Write Command 8.3.3. Preventing Flash/EEPROM Corruption 8.3.4. Interrupts 8.3.5. Sleep Mode Operation 8.3.6. Configuration Change Protection 8.4. Register Summary - NVMCTRL 8.5. Register Description 8.5.1. Control A 8.5.2. Control B 8.5.3. Status 8.5.4. Interrupt Control 8.5.5. Interrupt Flags 8.5.6. Data 8.5.7. Address 9. Clock Controller (CLKCTRL) 9.1. Features 9.2. Overview 9.2.1. Block Diagram - CLKCTRL 9.2.2. Signal Description 9.3. Functional Description 9.3.1. Sleep Mode Operation 9.3.2. Main Clock Selection and Prescaler 9.3.3. Main Clock After Reset 9.3.4. Clock Sources 9.3.4.1. Internal Oscillators 9.3.4.1.1. 20 MHz Oscillator (OSC20M) 9.3.4.1.1.1. OSC20M Stored Frequency Error Compensation 9.3.4.1.2. 32 KHz Oscillator (OSCULP32K) 9.3.4.2. External Clock Sources 9.3.4.2.1. 32.768 kHz Crystal Oscillator (XOSC32K) 9.3.4.2.2. External Clock (EXTCLK) 9.3.5. Configuration Change Protection 9.4. Register Summary - CLKCTRL 9.5. Register Description 9.5.1. Main Clock Control A 9.5.2. Main Clock Control B 9.5.3. Main Clock Lock 9.5.4. Main Clock Status 9.5.5. 20 MHz Oscillator Control A 9.5.6. 20 MHz Oscillator Calibration B 9.5.7. 32 KHz Oscillator Control A 9.5.8. 32.768 kHz Crystal Oscillator Control A 10. Sleep Controller (SLPCTRL) 10.1. Features 10.2. Overview 10.2.1. Block Diagram 10.3. Functional Description 10.3.1. Initialization 10.3.2. Operation 10.3.2.1. Sleep Modes 10.3.2.2. Wake-Up Time 10.3.3. Debug Operation 10.4. Register Summary - SLPCTRL 10.5. Register Description 10.5.1. Control A 11. Reset Controller (RSTCTRL) 11.1. Features 11.2. Overview 11.2.1. Block Diagram 11.2.2. Signal Description 11.3. Functional Description 11.3.1. Initialization 11.3.2. Operation 11.3.2.1. Reset Sources 11.3.2.1.1. Power-On Reset (POR) 11.3.2.1.2. Brown-Out Detector (BOD) Reset 11.3.2.1.3. Software Reset 11.3.2.1.4. External Reset 11.3.2.1.5. Watchdog Reset 11.3.2.1.6. Universal Program Debug Interface (UPDI) Reset 11.3.2.1.7. Domains Affected By Reset 11.3.2.2. Reset Time 11.3.3. Sleep Mode Operation 11.3.4. Configuration Change Protection 11.4. Register Summary - RSTCTRL 11.5. Register Description 11.5.1. Reset Flag Register 11.5.2. Software Reset Register 12. CPU Interrupt Controller (CPUINT) 12.1. Features 12.2. Overview 12.2.1. Block Diagram 12.3. Functional Description 12.3.1. Initialization 12.3.2. Operation 12.3.2.1. Enabling, Disabling, and Resetting 12.3.2.2. Interrupt Vector Locations 12.3.2.3. Interrupt Response Time 12.3.2.4. Interrupt Priority 12.3.2.4.1. Non-Maskable Interrupts (NMI) 12.3.2.4.2. High Priority Interrupt 12.3.2.4.3. Normal Priority Interrupts 12.3.2.4.3.1. Scheduling of Normal Priority Interrupts 12.3.2.4.3.1.1. Static Scheduling 12.3.2.4.3.1.2. Round Robin Scheduling 12.3.2.5. Compact Vector Table 12.3.3. Configuration Change Protection 12.4. Register Summary - CPUINT 12.5. Register Description 12.5.1. Control A 12.5.2. Status 12.5.3. Interrupt Priority Level 0 12.5.4. Interrupt Vector with Priority Level 1 13. Event System (EVSYS) 13.1. Features 13.2. Overview 13.2.1. Block Diagram 13.2.2. Signal Description 13.3. Functional Description 13.3.1. Initialization 13.3.2. Operation 13.3.2.1. Event User Multiplexer Setup 13.3.2.2. Event System Channel 13.3.2.3. Event Generators 13.3.2.4. Event Users 13.3.2.5. Synchronization 13.3.2.6. Software Event 13.3.3. Sleep Mode Operation 13.3.4. Debug Operation 13.4. Register Summary - EVSYS 13.5. Register Description 13.5.1. Channel Strobe 13.5.2. Channel Strobe 13.5.3. Channel n Generator Selection 13.5.4. User Channel Mux 14. Port Multiplexer (PORTMUX) 14.1. Overview 14.2. Register Summary - PORTMUX 14.3. Register Description 14.3.1. PORTMUX Control for Event System 14.3.2. PORTMUX Control for CCL 14.3.3. PORTMUX Control for USART 14.3.4. PORTMUX Control for TWI and SPI 14.3.5. PORTMUX Control for TCA 14.3.6. PORTMUX Control for TCB 15. I/O Pin Configuration (PORT) 15.1. Features 15.2. Overview 15.2.1. Block Diagram 15.2.2. Signal Description 15.3. Functional Description 15.3.1. Initialization 15.3.2. Operation 15.3.2.1. Basic Functions 15.3.2.2. Pin Configuration 15.3.2.3. Virtual Ports 15.3.2.4. Peripheral Override 15.3.3. Interrupts 15.3.4. Events 15.3.5. Sleep Mode Operation 15.4. Register Summary - PORTx 15.5. Register Description - Ports 15.5.1. Data Direction 15.5.2. Data Direction Set 15.5.3. Data Direction Clear 15.5.4. Data Direction Toggle 15.5.5. Output Value 15.5.6. Output Value Set 15.5.7. Output Value Clear 15.5.8. Output Value Toggle 15.5.9. Input Value 15.5.10. Interrupt Flags 15.5.11. Port Control 15.5.12. Pin n Control 15.6. Register Summary - VPORTx 15.7. Register Description - Virtual Ports 15.7.1. Data Direction 15.7.2. Output Value 15.7.3. Input Value 15.7.4. Interrupt Flag 16. Brown-Out Detector (BOD) 16.1. Features 16.2. Overview 16.2.1. Block Diagram 16.3. Functional Description 16.3.1. Initialization 16.3.2. Interrupts 16.3.3. Sleep Mode Operation 16.3.4. Configuration Change Protection 16.4. Register Summary - BOD 16.5. Register Description 16.5.1. Control A 16.5.2. Control B 16.5.3. VLM Control A 16.5.4. Interrupt Control 16.5.5. VLM Interrupt Flags 16.5.6. VLM Status 17. Voltage Reference (VREF) 17.1. Features 17.2. Overview 17.2.1. Block Diagram 17.3. Functional Description 17.3.1. Initialization 17.4. Register Summary - VREF 17.5. Register Description 17.5.1. Control A 17.5.2. Control B 18. Watchdog Timer (WDT) 18.1. Features 18.2. Overview 18.2.1. Block Diagram 18.2.2. Signal Description 18.3. Functional Description 18.3.1. Initialization 18.3.2. Clocks 18.3.3. Operation 18.3.3.1. Normal Mode 18.3.3.2. Window Mode 18.3.3.3. Configuration Protection and Lock 18.3.4. Sleep Mode Operation 18.3.5. Debug Operation 18.3.6. Synchronization 18.3.7. Configuration Change Protection 18.4. Register Summary - WDT 18.5. Register Description 18.5.1. Control A 18.5.2. Status 19. 16-bit Timer/Counter Type A (TCA) 19.1. Features 19.2. Overview 19.2.1. Block Diagram 19.2.2. Signal Description 19.3. Functional Description 19.3.1. Definitions 19.3.2. Initialization 19.3.3. Operation 19.3.3.1. Normal Operation 19.3.3.2. Double Buffering 19.3.3.3. Changing the Period 19.3.3.4. Compare Channel 19.3.3.4.1. Waveform Generation 19.3.3.4.2. Frequency (FRQ) Waveform Generation 19.3.3.4.3. Single-Slope PWM Generation 19.3.3.4.4. Dual-Slope PWM 19.3.3.4.5. Port Override for Waveform Generation 19.3.3.5. Timer/Counter Commands 19.3.3.6. Split Mode - Two 8-Bit Timer/Counters 19.3.4. Events 19.3.5. Interrupts 19.4. Sleep Mode Operation 19.5. Register Summary - TCAn in Normal Mode (SPLITM in TCAn.CTRLD=0) 19.6. Register Description - Normal Mode 19.6.1. Control A 19.6.2. Control B - Normal Mode 19.6.3. Control C - Normal Mode 19.6.4. Control D 19.6.5. Control Register E Clear - Normal Mode 19.6.6. Control Register E Set - Normal Mode 19.6.7. Control Register F Clear 19.6.8. Control Register F Set 19.6.9. Event Control 19.6.10. Interrupt Control Register - Normal Mode 19.6.11. Interrupt Flag Register - Normal Mode 19.6.12. Debug Control Register 19.6.13. Temporary Bits for 16-Bit Access 19.6.14. Counter Register - Normal Mode 19.6.15. Period Register - Normal Mode 19.6.16. Compare n Register - Normal Mode 19.6.17. Period Buffer Register 19.6.18. Compare n Buffer Register 19.7. Register Summary - TCAn in Split Mode (SPLITM in TCAn.CTRLD=1) 19.8. Register Description - Split Mode 19.8.1. Control A 19.8.2. Control B - Split Mode 19.8.3. Control C - Split Mode 19.8.4. Control D 19.8.5. Control Register E Clear - Split Mode 19.8.6. Control Register E Set - Split Mode 19.8.7. Interrupt Control Register - Split Mode 19.8.8. Interrupt Flag Register - Split Mode 19.8.9. Debug Control Register 19.8.10. Low Byte Timer Counter Register - Split Mode 19.8.11. High Byte Timer Counter Register - Split Mode 19.8.12. Low Byte Timer Period Register - Split Mode 19.8.13. High Byte Period Register - Split Mode 19.8.14. Compare Register n For Low Byte Timer - Split Mode 19.8.15. High Byte Compare Register n - Split Mode 20. 16-bit Timer/Counter Type B (TCB) 20.1. Features 20.2. Overview 20.2.1. Block Diagram 20.2.2. Signal Description 20.3. Functional Description 20.3.1. Definitions 20.3.2. Initialization 20.3.3. Operation 20.3.3.1. Modes 20.3.3.1.1. Periodic Interrupt Mode 20.3.3.1.2. Time-Out Check Mode 20.3.3.1.3. Input Capture on Event Mode 20.3.3.1.4. Input Capture Frequency Measurement Mode 20.3.3.1.5. Input Capture Pulse-Width Measurement Mode 20.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode 20.3.3.1.7. Single-Shot Mode 20.3.3.1.8. 8-Bit PWM Mode 20.3.3.2. Noise Canceler 20.3.3.3. Synchronized with TCAn 20.3.4. Events 20.3.5. Interrupts 20.3.6. Sleep Mode Operation 20.4. Register Summary - TCB 20.5. Register Description 20.5.1. Control A 20.5.2. Control B 20.5.3. Event Control 20.5.4. Interrupt Control 20.5.5. Interrupt Flags 20.5.6. Status 20.5.7. Debug Control 20.5.8. Temporary Value 20.5.9. Count 20.5.10. Capture/Compare 21. Real-Time Counter (RTC) 21.1. Features 21.2. Overview 21.2.1. Block Diagram 21.3. Clocks 21.4. RTC Functional Description 21.4.1. Initialization 21.4.1.1. Configure the Clock CLK_RTC 21.4.1.2. Configure RTC 21.4.2. Operation - RTC 21.4.2.1. Enabling, Disabling, and Resetting 21.5. PIT Functional Description 21.5.1. Initialization 21.5.2. Operation - PIT 21.5.2.1. Enabling, Disabling, and Resetting 21.5.2.2. PIT Interrupt Timing 21.6. Crystal Error Correction 21.7. Events 21.8. Interrupts 21.9. Sleep Mode Operation 21.10. Synchronization 21.11. Register Summary - RTC 21.12. Register Description 21.12.1. Control A 21.12.2. Status 21.12.3. Interrupt Control 21.12.4. Interrupt Flag 21.12.5. Temporary 21.12.6. Debug Control 21.12.7. Calibration 21.12.8. Clock Selection 21.12.9. Count 21.12.10. Period 21.12.11. Compare 21.12.12. Periodic Interrupt Timer Control A 21.12.13. Periodic Interrupt Timer Status 21.12.14. PIT Interrupt Control 21.12.15. PIT Interrupt Flag 21.12.16. Periodic Interrupt Timer Debug Control 22. Universal Synchronous and Asynchronous Receiver and Transmitter (USART) 22.1. Features 22.2. Overview 22.2.1. Block Diagram 22.2.2. Signal Description 22.3. Functional Description 22.3.1. Initialization 22.3.2. Operation 22.3.2.1. Clock Generation 22.3.2.1.1. Internal Clock Generation - The Fractional Baud Rate Generator 22.3.2.1.2. External Clock 22.3.2.1.3. Double Speed Operation 22.3.2.1.4. Synchronous Clock Operation 22.3.2.1.5. Master SPI Mode Clock Generation 22.3.2.2. Frame Formats 22.3.2.2.1. Parity 22.3.2.2.2. SPI Frame Formats 22.3.2.3. Data Transmission - USART Transmitter 22.3.2.3.1. Sending Frames 22.3.2.3.2. Disabling the Transmitter 22.3.2.4. Data Reception - USART Receiver 22.3.2.4.1. Receiving Frames 22.3.2.4.2. Receiver Error Flags 22.3.2.4.3. Parity Checker 22.3.2.4.4. Disabling the Receiver 22.3.2.4.5. Flushing the Receive Buffer 22.3.2.4.6. Asynchronous Data Reception 22.3.2.4.6.1. Asynchronous Clock Recovery 22.3.2.4.6.2. Asynchronous Data Recovery 22.3.2.4.7. Asynchronous Operational Range 22.3.2.5. USART in Master SPI mode 22.3.2.5.1. USART SPI vs. SPI 22.3.2.6. Half Duplex Operations 22.3.2.7. Start Frame Detection 22.3.2.8. Break Character Detection and Auto-Baud 22.3.2.9. Multiprocessor Communication Mode 22.3.2.9.1. Using Multiprocessor Communication Mode 22.3.2.10. IRCOM Mode of Operation 22.3.2.10.1. Overview 22.3.2.10.2. Block Diagram 22.3.2.10.3. IRCOM and Event System 22.3.3. Events 22.3.4. Interrupts 22.4. Register Summary - USARTn 22.5. Register Description 22.5.1. Receiver Data Register Low Byte 22.5.2. Receiver Data Register High Byte 22.5.3. Transmit Data Register Low Byte 22.5.4. Transmit Data Register High Byte 22.5.5. USART Status Register 22.5.6. Control A 22.5.7. Control B 22.5.8. Control C - Async Mode 22.5.9. Control C - Master SPI Mode 22.5.10. Baud Register 22.5.11. Debug Control Register 22.5.12. IrDA Control Register 22.5.13. IRCOM Transmitter Pulse Length Control Register 22.5.14. IRCOM Receiver Pulse Length Control Register 23. Serial Peripheral Interface (SPI) 23.1. Features 23.2. Overview 23.2.1. Block Diagram 23.2.2. Signal Description 23.3. Functional Description 23.3.1. Initialization 23.3.2. Operation 23.3.2.1. Master Mode Operation 23.3.2.1.1. SS Pin Functionality in Master Mode - Multi-Master Support 23.3.2.1.2. Normal Mode 23.3.2.1.3. Buffer Mode 23.3.2.2. Slave Mode 23.3.2.2.1. SS Pin Functionality in Slave Mode 23.3.2.2.2. Normal Mode 23.3.2.2.3. Buffer Mode 23.3.2.3. Data Modes 23.3.2.4. Events 23.3.2.5. Interrupts 23.4. Register Summary - SPIn 23.5. Register Description 23.5.1. Control A 23.5.2. Control B 23.5.3. Interrupt Flags - Normal Mode 23.5.4. Interrupt Flags - Buffer Mode 23.5.5. Data 24. Two-Wire Interface (TWI) 24.1. Features 24.2. Overview 24.2.1. Block Diagram 24.2.2. Signal Description 24.3. Functional Description 24.3.1. Initialization 24.3.2. General TWI Bus Concepts 24.3.2.1. Start and Stop Conditions 24.3.2.2. Bit Transfer 24.3.2.3. Address Packet 24.3.2.4. Data Packet 24.3.2.5. Transaction 24.3.2.6. Clock and Clock Stretching 24.3.2.7. Arbitration 24.3.2.8. Synchronization 24.3.3. TWI Bus State Logic 24.3.4. Operation 24.3.4.1. Electrical Characteristics 24.3.4.2. TWI Master Operation 24.3.4.2.1. Clock Generation 24.3.4.2.2. Transmitting Address Packets 24.3.4.2.2.1. Case M1: Arbitration Lost or Bus Error during Address Packet 24.3.4.2.2.2. Case M2: Address Packet Transmit Complete - Address not Acknowledged by Slave 24.3.4.2.2.3. Case M3: Address Packet Transmit Complete - Direction Bit Cleared 24.3.4.2.2.4. Case M4: Address Packet Transmit Complete - Direction Bit Set 24.3.4.2.3. Transmitting Data Packets 24.3.4.2.4. Receiving Data Packets 24.3.4.2.5. Quick Command Mode 24.3.4.3. TWI Slave Operation 24.3.4.3.1. Receiving Address Packets 24.3.4.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set 24.3.4.3.1.2. Case S2: Address Packet Accepted - Direction Bit Cleared 24.3.4.3.1.3. Case S3: Collision 24.3.4.3.1.4. Case S4: STOP Condition Received 24.3.4.3.2. Receiving Data Packets 24.3.4.3.3. Transmitting Data Packets 24.3.4.4. Smart Mode 24.3.5. Interrupts 24.3.6. Sleep Mode Operation 24.4. Register Summary - TWIn 24.5. Register Description 24.5.1. Control A 24.5.2. Dual Mode Control Configuration 24.5.3. Debug Control 24.5.4. Master Control A 24.5.5. Master Control B 24.5.6. Master Status 24.5.7. Master Baud Rate 24.5.8. Master Address 24.5.9. Master DATA 24.5.10. Slave Control A 24.5.11. Slave Control B 24.5.12. Slave Status 24.5.13. Slave Address 24.5.14. Slave Data 24.5.15. Slave Address Mask 25. Cyclic Redundancy Check Memory Scan (CRCSCAN) 25.1. Features 25.2. Overview 25.2.1. Block Diagram 25.3. Functional Description 25.3.1. Initialization 25.3.2. Operation 25.3.2.1. Checksum 25.3.3. Interrupts 25.3.4. Sleep Mode Operation 25.3.5. Debug Operation 25.4. Register Summary - CRCSCAN 25.5. Register Description 25.5.1. Control A 25.5.2. Control B 25.5.3. Status 26. CCL – Configurable Custom Logic 26.1. Features 26.2. Overview 26.2.1. Block Diagram 26.2.2. Signal Description 26.2.2.1. CCL Input Selection MUX 26.3. Functional Description 26.3.1. Initialization 26.3.2. Operation 26.3.2.1. Enabling, Disabling, and Resetting 26.3.2.2. Look-Up Table Logic 26.3.2.3. Truth Table Inputs Selection 26.3.2.4. Filter 26.3.2.5. Edge Detector 26.3.2.6. Sequential Logic 26.3.2.7. Clock Source Settings 26.3.3. Interrupts 26.3.4. Events 26.3.5. Sleep Mode Operation 26.4. Register Summary - CCL 26.5. Register Description 26.5.1. Control A 26.5.2. Sequential Control 0 26.5.3. Interrupt Control 0 26.5.4. Interrupt Flag 26.5.5. LUT n Control A 26.5.6. LUT n Control B 26.5.7. LUT n Control C 26.5.8. TRUTHn 27. Analog Comparator (AC) 27.1. Features 27.2. Overview 27.2.1. Block Diagram 27.2.2. Signal Description 27.3. Functional Description 27.3.1. Initialization 27.3.2. Operation 27.3.2.1. Input Hysteresis 27.3.2.2. Input Sources 27.3.2.2.1. Pin Inputs 27.3.2.2.2. Internal Inputs 27.3.2.3. Power Modes 27.3.2.4. Signal Compare and Interrupt 27.3.3. Events 27.3.4. Interrupts 27.3.5. Sleep Mode Operation 27.4. Register Summary - AC 27.5. Register Description 27.5.1. Control A 27.5.2. Mux Control 27.5.3. DAC Voltage Reference 27.5.4. Interrupt Control 27.5.5. Status 28. Analog-to-Digital Converter (ADC) 28.1. Features 28.2. Overview 28.2.1. Block Diagram 28.2.2. Signal Description 28.2.2.1. Definitions 28.3. Functional Description 28.3.1. Initialization 28.3.1.1. I/O Lines and Connections 28.3.2. Operation 28.3.2.1. Starting a Conversion 28.3.2.2. Clock Generation 28.3.2.3. Conversion Timing 28.3.2.4. Changing Channel or Reference Selection 28.3.2.4.1. ADC Input Channels 28.3.2.4.2. ADC Voltage Reference 28.3.2.4.3. Analog Input Circuitry 28.3.2.5. ADC Conversion Result 28.3.2.6. Temperature Measurement 28.3.2.7. Window Comparator Mode 28.3.3. Events 28.3.4. Interrupts 28.3.5. Sleep Mode Operation 28.4. Register Summary - ADCn 28.5. Register Description 28.5.1. Control A 28.5.2. Control B 28.5.3. Control C 28.5.4. Control D 28.5.5. Control E 28.5.6. Sample Control 28.5.7. MUXPOS 28.5.8. Command 28.5.9. Event Control 28.5.10. Interrupt Control 28.5.11. Interrupt Flags 28.5.12. Debug Run 28.5.13. Temporary 28.5.14. Result 28.5.15. Window Comparator Low Threshold 28.5.16. Window Comparator High Threshold 28.5.17. Calibration 29. Unified Program and Debug Interface (UPDI) 29.1. Features 29.2. Overview 29.2.1. Block Diagram 29.2.2. Clocks 29.2.3. Power Management 29.3. Functional Description 29.3.1. Principle of Operation 29.3.1.1. UPDI UART 29.3.1.2. BREAK Character 29.3.2. Operation 29.3.2.1. UPDI Enable 29.3.2.2. UPDI Disable 29.3.2.3. UPDI Communication Error Handling 29.3.2.4. Direction Change 29.3.3. UPDI Instruction Set 29.3.3.1. LDS - Load Data from Data Space Using Direct Addressing 29.3.3.2. STS - Store Data to Data Space Using Direct Addressing 29.3.3.3. LD - Load Data from Data Space Using Indirect Addressing 29.3.3.4. ST - Store Data from Data Space Using Indirect Addressing 29.3.3.5. LCDS - Load Data from Control and Status Register Space 29.3.3.6. STCS (Store Data to Control and Status Register Space) 29.3.3.7. REPEAT - Set Instruction Repeat Counter 29.3.3.8. KEY - Set Activation KEY 29.3.4. System Clock Measurement with UPDI 29.3.5. Interbyte Delay 29.3.6. System Information Block 29.3.7. Enabling of KEY Protected Interfaces 29.3.7.1. Chip Erase 29.3.7.2. NVM Programming 29.3.7.3. User Row Programming 29.3.8. Events 29.3.9. Sleep Mode Operation 29.4. Register Summary - UPDI 29.5. Register Description 29.5.1. Status A 29.5.2. Status B 29.5.3. Control A 29.5.4. Control B 29.5.5. ASI Key Status 29.5.6. ASI Reset Request 29.5.7. ASI Control A 29.5.8. ASI System Control A 29.5.9. ASI System Status 29.5.10. ASI CRC Status 30. Instruction Set Summary 31. Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service