LYTSwitch-6 Diode D16 isolates C3 rectified AC input from C4, also provides doubler. Input capacitor voltage should be sized to meet these current path for the charging of the bulk capacitor C4 especial y at criteria for AC input designs. low line which improves efficiency. Free-wheel diodes D1 and D17 2. Efficiency assumptions depend on power level. Smallest device provides path for the energy stored in the PFC inductor that is power level assumes efficiency >84% increasing to >89% for the transferred to the secondary-side during MOSFET turn-off time. D1 largest device. and D17 are connected in series to withstand the voltage resonance 3. Transformer primary inductance tolerance of ±10%. ring from the PFC inductor when the MOSFET turns off. 4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at minimum input voltage for universal line and KP = 1 for high input During no-load or light load condition (i.e. <10% load) the energy line designs. stored in the PFC inductor is more than what the secondary load 5. Maximum conduction loss for adapters is limited to 0.6 W, 0.8 W requires, the excess energy from the PFC inductor is recycled to the for open frame designs. bulk capacitor C4 which boosts up the voltage level. Zener-resistor 6. Increased current limit is selected for peak and open frame power clamp, VR1 and VR2 in series with R47 that is connected across the columns and standard current limit for adapter columns. bulk capacitor C4 were employed to limit the voltage from rising 7. The part is board mounted with SOURCE pins soldered to a above C4 voltage rating. The Zener clamp voltage should be less sufficient area of copper and/or a heat sink to keep the SOURCE than or equal to the 450 V maximum voltage rating of bulk capacitor pin temperature at or below 110 °C. C4. In the event of line voltage surge or transient, in order to protect 8. Ambient temperature of 50 °C for open frame designs and 40 °C the internal mosfet of the IC from Drain overvoltage, the line over- for sealed adapters. voltage shutdown of the IC through the INPUT OVERVOLTAGE pin 9. Below a value of 1, KP is the ratio of ripple to peak primary resistor (R5 and R45) was set to trigger at around 460 V. current. To prevent reduced power delivery, due to premature Secondary Stage termination of switching cycles, a transient KP limit of ≥0.6 is The secondary-side control of the LYTSwitch-6 IC provides constant recommended. This prevents the initial current limit (IINT) from output voltage and constant output current. The secondary of the being exceeded at MOSFET turn-on. transformer is rectified by D10 and filtered by the output capacitors 10. It is unique feature in LYTSwitch-6 device that a designer can set C16 and C18. Adding an RC snubber (R48 and C14) across the output the operating switching frequency between 25 kHz to 95 kHz diode reduces voltage stress across it. The SYNCHRONOUS depending on the transformer design. One of the ways to RECTIFIER DRIVE pin is connected to the SECONDARY GROUND pin effectively lower device temperature is to design the transformer to al ow the use of a cheaper ultrafast output diode instead of using to operate at low switching frequency; a good starting point is an SR FET. 50 kHz. The secondary-side of the IC is self-powered from either the Primary-Side Overvoltage Protection secondary winding forward voltage via FORWARD pin or the output Primary-side output overvoltage protection provided by the voltage via OUTPUT VOLTAGE pin. Capacitor C13 connected to the LYTSwitch-6 IC uses an internal latch that is triggered by a threshold SECONDARY BYPASS pin of LYTSwitch-6 IC (U1) provides decoupling current of I into the PRIMARY BYPASS pin. For the bypass capacitor SD for the internal circuitry. In this design, the secondary-side of the IC to be effective as a high frequency filter, the capacitor should be has to be powered from a lower voltage auxiliary supply (winding FL3 located as close as possible to the SOURCE and PRIMARY BYPASS and FL4) within the maximum voltage rating of the OUTPUT VOLTAGE pins of the device. pin, consequently the FORWARD pin has to be connected from the The primary sensed OVP function can be realized by connecting a same output for good regulation and efficiency. The auxiliary supply series combination of a Zener diode, a resistor and a blocking diode is rectified and filtered by D11 and C15 respectively. from the rectified and filtered bias winding voltage supply to the During constant voltage operation, the output voltage regulation is PRIMARY BYPASS pin (see Figure 11-a). The rectified and filtered bias achieved through sensing the output voltage via network divider winding output voltage may be higher than expected (up to 1.5X or resistors R29 and R30. The voltage across R30 is monitored at the 2X the desired value) dependent on the coupling of the bias winding FEEDBACK pin and compared to an internal reference voltage with the output winding and the resulting ringing on the bias winding threshold of 1.265 V to maintain tight regulation. Bypass capacitor voltage waveform. It is therefore recommended that the rectified C19 is placed across placed across FEEDBACK and SECONDARY bias winding voltage be measured. This measurement should be GROUND pins to filter high frequency noise that may couple to the ideal y done at the lowest input voltage and with highest load on the feedback signal and cause unwanted behavior such as pulse grouping. output. This measured voltage should be used to select the components required to achieve primary sensed OVP. It is During constant current operation, the maximum output current is set recommended that a Zener diode with a clamping voltage by the sense resistors R43 and R49 , the voltage across the sense approximately 6 V lower than the bias winding rectified voltage at resistor is compared to the ISENSE pin’s internal reference threshold which OVP is expected to be triggered be selected. A forward of 35 mV to maintain constant current regulation. Diode D13 in voltage drop of 1 V can be assumed for the blocking diode. A small paral el with the current sense resistors clamps the voltage across the signal standard recovery diode is recommended. The blocking diode ISENSE and SECONDARY GROUND pin and bypasses the high current prevents any reverse current charging the bias capacitor during surge from the output capacitor during output short circuit conditions, start-up. Final y, the value of the series resistor required can be thus preventing the current sense resistors from damage. calculated such that a current higher than I will flow into the SD Key Applications Design Considerations PRIMARY BYPASS pin during an output overvoltage event. Output Power TableSecondary-Side Overvoltage Protection The data sheet output power table (Table 1) represents the maximum The secondary-side output overvoltage protection provided by the practical continuous output power level that can be obtained under LYTSwitch-6 IC uses an internal auto-restart circuit that is triggered the fol owing conditions: by an input current exceeding a threshold of I into the BPS(SD) SECONDARY BYPASS pin. The direct output sensed OVP function can 1. The minimum DC input voltage is 90 V or higher for 85 VAC input, be realized by connecting a Zener diode from the output to the 220 V or higher for 230 VAC input or 115 VAC with a voltage- SECONDARY BYPASS pin. The Zener diode voltage needs to be the 10 Rev. E 02/18 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description LYTSwitch-6 Functional Description Primary Controller Secondary Controller Application Example Key Applications Design Considerations Primary-Side Components of LYTSwitch-6 Secondary-Side Components of f LYTSwitch-6 Recommendations for Circuit Board Layout Recommended Position of InSOP-24D Package with Respect to Transformer Quick Design Checklist Other Applications Design Example PCB Layout Example Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Curves InSOP-24D Package Drawing MSL Table ESD and Latch-Up Table Part Ordering Information