Datasheet LAN9353 (Microchip) - 4

LAN9353 1.0 PREFACE 1.1 General Terms TABLE 1-1: GENERAL TERMS Term Description 10BASE-T
10 Mbps Ethernet, IEEE 802.3 compliant
100BASE-TX
100 Mbps Fast Ethernet, IEEE802.3u compliant
ADC
Analog-to-Digital Converter
ALR
Address Logic Resolution
AN
Auto-Negotiation
BLW
Baseline Wander
BM
Buffer Manager - Part of the switch fabric
BPDU
Bridge Protocol Data Unit - Messages which carry the Spanning Tree Protocol informa- tion
Byte
8 bits
CSMA/CD
Carrier Sense Multiple Access/Collision Detect
CSR
Control and Status Registers
CTR
Counter
DA
Destination Address
DWORD
32 bits
EPC
EEPROM Controller
FCS
Frame Check Sequence - The extra checksum characters added to the end of an Ethernet frame, used for error detection and correction.
FIFO
First In First Out buffer
FSM
Finite State Machine
GPIO
General Purpose I/O
Host
External system (Includes processor, application software, etc.)
IGMP
Internet Group Management Protocol
Inbound
Refers to data input to the device from the host
Level-Triggered Sticky Bit
This type of status bit is set whenever the condition that it represents is asserted. The bit remains set until the condition is no longer true and the status bit is cleared by writ- ing a zero.
lsb
Least Significant Bit
LSB
Least Significant Byte
LVDS
Low Voltage Differential Signaling
MDI
Medium Dependent Interface
MDIX
Media Independent Interface with Crossover
MII
Media Independent Interface
MIIM
Media Independent Interface Management
MIL
MAC Interface Layer
MLD
Multicast Listening Discovery
MLT-3
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”.
msb
Most Significant Bit
MSB
Most Significant Byte DS00001925A-page 4  2015 Microchip Technology Inc. Document Outline Highlights Target Applications Key Benefits 1.0 Preface TABLE 1-1: General Terms TABLE 1-2: Buffer Types TABLE 1-3: Register Nomenclature 2.0 General Description FIGURE 2-1: Internal Block Diagram 3.0 Pin Descriptions and Configuration FIGURE 3-1: 64-QFN Pin Assignments (Top View) TABLE 3-1: 64-QFN Package Pin Assignments FIGURE 3-2: 64-TQFP-EP Pin Assignments (Top View) TABLE 3-2: 64-TQFP-EP Package Pin Assignments TABLE 3-3: LAN Port A Pin Descriptions TABLE 3-4: LAN Port B Pin Descriptions TABLE 3-5: LAN Port A & B Power and Common Pin Descriptions TABLE 3-6: Switch Port 0 MII/RMII & Configuration Strap Pin Descriptions TABLE 3-7: Switch Port 1 RMII & Configuration Strap Pin Descriptions TABLE 3-8: I2C Management Pin Descriptions TABLE 3-9: EEPROM Pin Descriptions TABLE 3-10: GPIO, LED & Configuration Strap Pin Descriptions TABLE 3-11: Miscellaneous Pin Descriptions TABLE 3-12: JTAG Pin Descriptions TABLE 3-13: Core and I/O Power Pin Descriptions 4.0 Power Connections FIGURE 4-1: Power Connections - Regulators Enabled FIGURE 4-2: Power Connections - Regulators Disabled 5.0 Register Map FIGURE 5-1: Register Address Map TABLE 5-1: System Control and Status Registers TABLE 5-2: Read After Write Timing Rules TABLE 5-3: Read After Read Timing Rules 6.0 Clocks, Resets, and Power Management TABLE 6-1: Reset Sources and Affected Device Functionality FIGURE 6-1: PME Interrupt Signal Generation TABLE 6-2: Power Management States 7.0 Configuration Straps TABLE 7-1: Soft-Strap Configuration Strap Definitions TABLE 7-2: Hard-Strap Configuration Strap Definitions TABLE 7-3: Port 0 Mode Strap Mapping TABLE 7-4: Port 1 Mode Strap Mapping 8.0 System Interrupts FIGURE 8-1: Functional Interrupt Hierarchy TABLE 8-1: Interrupt Registers 9.0 Ethernet PHYs TABLE 9-1: Default PHY Serial MII Addressing FIGURE 9-1: Physical PHY Block Diagram FIGURE 9-2: 100BASE-TX Transmit Data Path TABLE 9-2: 4B/5B Code Table FIGURE 9-3: 100BASE-TX Receive Data Path FIGURE 9-4: Direct Cable Connection vs. Cross-Over Cable Connection TABLE 9-3: Interrupt Management Table TABLE 9-4: Alternative Interrupt Mode Management Table TABLE 9-5: Wakeup Generation Cases FIGURE 9-5: TDR Usage Flow Diagram TABLE 9-6: TDR Propagation Constants TABLE 9-7: Typical Measurement Error for Open Cable (+/- Meters) TABLE 9-8: Typical Measurement Error for Shorted Cable (+/- Meters) TABLE 9-9: Match Case Estimated Cable Length (CBLN) Lookup FIGURE 9-6: Near-end Loopback Block Diagram FIGURE 9-7: Connection Loopback Block Diagram TABLE 9-10: 100BASE-FX LOS, SD and TP Copper Selection PHY A TABLE 9-11: 100BASE-FX LOS, SD and TP Copper Selection PHY B FIGURE 9-8: Physical PHY External Access Timing TABLE 9-12: Physical PHY External Access Timing Values TABLE 9-13: Physical PHY A and B MII Serially Accessible Control and Status Registers TABLE 9-14: 10BASE-T Full Duplex Advertisement Default Value TABLE 9-15: 10BASE-T Half Duplex Advertisement Bit Default Value TABLE 9-16: MODE[2:0] Definitions TABLE 9-17: Auto-MDIX Enable and Auto-MDIX State Bit Functionality TABLE 9-18: MDIX Strap Functionality TABLE 9-19: MMD Registers FIGURE 9-9: Virtual PHY Timing TABLE 9-20: Virtual PHY Timing Values TABLE 9-21: Virtual PHY MII Serially Addressable Register Index TABLE 9-22: Emulated Link Partner Pause Flow Control Ability Default Values TABLE 9-23: Emulated Link Partner Default Advertised Ability 10.0 Switch Fabric FIGURE 10-1: ALR Table Entry Structure FIGURE 10-2: Switch Engine Transmit Queue Selection FIGURE 10-3: Switch Engine Transmit Queue Calculation FIGURE 10-4: VLAN Table Entry Structure TABLE 10-1: Spanning Tree States TABLE 10-2: Typical Ingress Rate Settings FIGURE 10-5: Switch Engine Ingress Flow Priority Selection FIGURE 10-6: Switch Engine Ingress Flow Priority Calculation TABLE 10-3: Typical Broadcast Rate Settings TABLE 10-4: Typical Egress Rate Settings FIGURE 10-7: Hybrid Port Tagging and Un-Tagging TABLE 10-5: Switch Fabric Flow Control Enable Logic FIGURE 10-8: Switch Fabrics CSR Write Access Flow Diagram FIGURE 10-9: Switch Fabrics CSR Read Access Flow Diagram TABLE 10-6: Switch Fabric Interface Logic Registers TABLE 10-7: SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH and EEPROM Byte Ordering FIGURE 10-10: Example SWITCH_MAC_ADDL, SWITCH_MAC_ADDRH and EEPROM Setup TABLE 10-8: Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map TABLE 10-9: Indirectly Accessible Switch Control and Status Registers TABLE 10-10: Metering/Color Table Register Descriptions 11.0 I2C Slave Controller 11.1 Functional Overview 11.2 I2C Overview 11.3 I2C Slave Operation 11.3.1 I2C Slave Command Format 11.3.2 Device Initialization 11.3.2.1 I2C Slave Read Polling for Initialization Complete 11.3.3 Access During and Following Power Management 11.3.4 I2C Slave Read Sequence 11.3.5 I2C Slave Write Sequence 12.0 I2C Master EEPROM Controller FIGURE 12-1: I2C Cycle FIGURE 12-2: I2C Master Timing TABLE 12-1: I2C Master Timing Values TABLE 12-2: I2C EEPROM Size Ranges FIGURE 12-3: I2C EEPROM Addressing FIGURE 12-4: I2C EEPROM Byte Read FIGURE 12-5: I2C EEPROM Sequential Byte Reads FIGURE 12-6: I2C EEPROM Byte Write FIGURE 12-7: EEPROM Access Flow Diagram TABLE 12-3: EEPROM Contents Format Overview FIGURE 12-8: EEPROM Loader Flow Diagram TABLE 12-4: EEPROM Configuration Bits TABLE 12-5: I2C Master EEPROM Controller Registers 13.0 MII Data Interfaces 13.1 Port 0 Data Path 13.1.1 Port 0 MII MAC Mode 13.1.2 Port 0 RMII MAC Mode 13.1.2.1 Reference Clock Selection 13.1.2.2 Clock Drive Strength 13.1.3 Port 0 MII PHY Mode 13.1.3.1 Isolate 13.1.3.2 Turbo Operation 13.1.3.3 Clock Drive Strength 13.1.3.4 Signal Quality Error (SQE) Heartbeat Test 13.1.3.5 Collision Test 13.1.3.6 Loopback 13.1.4 Port 0 RMII PHY Mode 13.1.4.1 Isolate 13.1.4.2 Reference Clock Selection 13.1.4.3 Clock Drive Strength 13.1.4.4 Signal Quality Error (SQE) Heartbeat Test 13.1.4.5 Collision Test 13.1.4.6 Loopback Mode 13.2 Port 1 Data Path 13.2.1 Port 1 Internal PHY Mode 13.2.2 Port 1 RMII MAC Mode 13.2.2.1 Reference Clock Selection 13.2.2.2 Clock Drive Strength 13.2.3 Port 1 RMII PHY Mode 13.2.3.1 Isolate 13.2.3.2 Reference Clock Selection 13.2.3.3 Clock Drive Strength 13.2.3.4 Signal Quality Error (SQE) Heartbeat Test 13.2.3.5 Collision Test 13.2.3.6 Loopback Mode 13.3 Port 2 Data Path 13.3.1 Port 2 Internal PHY Mode 13.4 Switch Fabric Timing Requirements 13.4.1 MII Interface Timing (MAC Mode) 13.4.2 MII Interface Timing (PHY Mode) 13.4.3 Turbo MII Interface Timing (MAC Mode) 13.4.4 Turbo MII Interface Timing (PHY Mode) 13.4.5 RMII Interface Timing (MAC Mode) 13.4.6 RMII Interface Timing (PHY Mode) 14.0 MII Management 14.1 Functional Overview 14.2 SMI Slave Controller 14.2.1 Device Initialization 14.2.2 Access During and Following Power Management 14.2.3 SMI Slave Command Format 14.2.3.1 Read Sequence 14.2.3.2 Write Sequence 14.2.4 SMI Timing Requirements 14.3 PHY Management Interface (PMI) 14.3.1 PMI Slave Command Format 14.3.2 PHY Register Host Access 14.3.3 EEPROM Loader PHY Register Access 14.3.4 PMI Timing Requirements 14.3.5 PHY Management Interface (PMI) Registers 14.3.5.1 PHY Management Interface Data Register (PMI_DATA) 14.3.5.2 PHY Management Interface Access Register (PMI_ACCESS) 14.4 MII Management Multiplexer 14.4.1 Port 0 Management Path Configurations 14.4.1.1 Port 0 MAC Mode SMI Managed 14.4.1.2 Port 0 MAC Mode SMI Managed - Device Initialization 14.4.1.3 Port 0 PHY Mode SMI Managed 14.4.1.4 Port 0 PHY Mode SMI Managed - Device Initialization 14.4.1.5 Port 0 MAC Mode I2C Managed 14.4.1.6 Port 0 PHY Mode I2C Managed 14.4.2 Port 1 Management Path Configurations 14.4.2.1 Port 1 Internal PHY Mode I2C or SMI Managed 14.4.2.2 Port 1 MAC Mode I2C or SMI Managed 14.4.2.3 Port 1 PHY Mode I2C or SMI Managed 15.0 IEEE 1588 FIGURE 15-1: 1588 Clock Block Diagram FIGURE 15-2: 1588 Clock Event Block Diagram TABLE 15-1: 1588 Control and Status Registers 16.0 General Purpose Timer & Free-Running Clock TABLE 16-1: Miscellaneous Registers 17.0 GPIO/LED Controller TABLE 17-1: LED Operation as a Function of LED_FUN[2:0] = 000b - 011b TABLE 17-2: LED Operation as a Function of LED_FUN[2:0] = 100b - 111b TABLE 17-3: GPIO/LED Registers 18.0 Miscellaneous TABLE 18-1: Miscellaneous Registers 19.0 JTAG TABLE 19-1: IEEE 1149.1 Op Codes FIGURE 19-1: JTAG Timing TABLE 19-2: JTAG Timing Values 20.0 Operational Characteristics TABLE 20-1: 64-PIN QFN Package Thermal Parameters TABLE 20-2: 64-PIN TQFP-EP Package Thermal Parameters TABLE 20-3: Maximum Power Dissipation TABLE 20-4: Current Consumption and Power Dissipation (Regs. Disabled) TABLE 20-5: Current Consumption and Power Dissipation (Regs. Enabled) TABLE 20-6: Non-Variable I/O DC Electrical Characteristics TABLE 20-7: Variable I/O DC Electrical Characteristics TABLE 20-8: 100BASE-TX Transceiver Characteristics TABLE 20-9: 10BASE-T Transceiver Characteristics FIGURE 20-1: Output Equivalent Test Load FIGURE 20-2: Power Sequence Timing - Internal Regulators FIGURE 20-3: Power Sequence Timing - External Regulators TABLE 20-10: Power Sequencing Timing Values FIGURE 20-4: RST# Pin Configuration Strap Latching Timing TABLE 20-11: RST# Pin Configuration Strap Latching Timing Values FIGURE 20-5: Power-On Configuration Strap Latching Timing TABLE 20-12: Power-On Configuration Strap Latching Timing Values TABLE 20-13: Crystal Specifications 21.0 Package Outlines FIGURE 21-1: 64-QFN Package FIGURE 21-2: 64-QFN Package Dimensions FIGURE 21-3: 64-TQFP-EP Package 22.0 Revision History TABLE 22-1: Revision History The Microchip Web Site Product Identification System Worldwide Sales and Service