Datasheet KS8995XA (Microchip) - 4

Micrel, Inc. KS8995XA Contents
System Level Applications. 6
Pin Configuration . 8
Pin Description (by Number). 9
Pin Description (by Name) . 14
Introduction . 19
Functional Overview: Physical Layer Transceiver . 19
100BASE-TX Transmit. 19
100BASE-TX Receive. 19
PLL Clock Synthesizer. 19
Scrambler/De-Scrambler (100BASE-TX only). 19
100BASE-FX Operation. 20
100BASE-FX Signal Detection . 20
100BASE-FX Far End Fault. 20
10BASE-T Transmit . 20
10BASE-T Receive . 20
Power Management. 20
MDI/MDI-X Auto Crossover . 20
Auto-Negotiation . 20
Functional Overview: Switch Core . 21
Address Look-Up . 21
Learning . 21
Migration . 21
Aging . 21
Switching Engine . 22
Media Access Controller (MAC) Operation. 22
Inter-Packet Gap (IPG) . 22
Backoff Algorithm . 22
Late Collision . 22
Illegal Frames . 22
Flow Control . 22
Half-Duplex Back Pressure . 22
Broadcast Storm Protection . 23
MII Interface Operation . 24
SNI Interface Operation . 26
Advanced Functionality. 26
QoS Support . 26
Rate Limit Support . 28
Configuration Interface. 29
2
I C Master Serial Bus Configuration . 29
MII Management Interface (MIIM) . 29
Register Map. 30
Global Registers . 30
Register 0 (0x00): Chip ID0 . 30
Register 1 (0x01): Chip ID1/Start Switch . 30
Register 2 (0x02): Global Control 0 . 30
Register 3 (0x03): Global Control 1 . 31
Register 4 (0x04): Global Control 2 . 32
Register 5 (0x05): Global Control 3 . 33
Register 6 (0x06): Global Control 4 . 33
Register 7 (0x07): Global Control 5 . 34
Register 8 (0x08): Global Control 6 . 34
Register 9 (0x09): Global Control 7 . 34
Register 10 (0x0A): Global Control 8 . 34 September 2008 4 M9999-091508