Datasheet KS8995X (Microchip) - 10
| Fabricante | Microchip |
| Descripción | Integrated 5-Port 10/100 QoS Switch |
| Páginas / Página | 51 / 10 |
| Formato / tamaño de archivo | PDF / 224 Kb |
| Idioma del documento | Inglés |
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KS8995X Micrel Pin Number Pin Name Type(1) Port 63 PMRXD2 Ipd/O 5 PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure. 64 PMRXD1 Ipd/O 5 PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets. 65 PMRXD0 Ipd/O 5 PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement. 66 PMRXER Ipd/O 5 PHY[5] MII receive error. Strap option: PD (default) = packet size
1518/1522 bytes; PU = 1536 bytes. 67 PCRS Ipd/O 5 PHY[5] MII carrier sense/force duplex mode. See “Register 28.” 68 PCOL Ipd/O 5 PHY[5] MII collision detect/force flow control. See “Register 18.” 69 SMTXEN Ipd Switch MII transmit enable 70 SMTXD3 Ipd Switch MII transmit bit 3 71 SMTXD2 Ipd Switch MII transmit bit 2 72 SMTXD1 Ipd Switch MII transmit bit 1 73 SMTXD0 Ipd Switch MII transmit bit 0 74 SMTXER Ipd Switch MII transmit error 75 SMTXC I/O Switch MII transmit clock. PHY or MAC mode MII. 76 GNDD Gnd Digital ground 77 VDDIO P 78 SMRXC I/O 79 SMRXDV Ipd/O Switch MII receive data valid 80 SMRXD3 Ipd/O Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control. 81 SMRXD2 Ipd/O Switch MII receive bit 2. Strap option: PD (default) = Switch MII in
full-duplex mode; PU = Switch MII in half-duplex mode. 82 SMRXD1 Ipd/O Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode. 83 SMRXD0 Ipd/O Switch MII receive bit 0; Strap option: see “Register 11[1].” 84 SCOL Ipd/O Switch MII collision detect 85 SCRS Ipd/O Switch mode carrier sense Pin Function 3.3/2.5V digital VDD for digital I/O circuitry.
Switch MII receive clock. PHY or MAC mode MII. Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/internal pull-up
Ipd = Input w/internal pull-down
Ipd/O = Input w/internal pull-down during reset, output pin otherwise
Ipu/O = Input w/internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pull-down
Otri = Output tristated M9999-120403 10 December 2003
pressure; PU = enable back pressure. 64 PMRXD1 Ipd/O 5 PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets. 65 PMRXD0 Ipd/O 5 PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement. 66 PMRXER Ipd/O 5 PHY[5] MII receive error. Strap option: PD (default) = packet size
1518/1522 bytes; PU = 1536 bytes. 67 PCRS Ipd/O 5 PHY[5] MII carrier sense/force duplex mode. See “Register 28.” 68 PCOL Ipd/O 5 PHY[5] MII collision detect/force flow control. See “Register 18.” 69 SMTXEN Ipd Switch MII transmit enable 70 SMTXD3 Ipd Switch MII transmit bit 3 71 SMTXD2 Ipd Switch MII transmit bit 2 72 SMTXD1 Ipd Switch MII transmit bit 1 73 SMTXD0 Ipd Switch MII transmit bit 0 74 SMTXER Ipd Switch MII transmit error 75 SMTXC I/O Switch MII transmit clock. PHY or MAC mode MII. 76 GNDD Gnd Digital ground 77 VDDIO P 78 SMRXC I/O 79 SMRXDV Ipd/O Switch MII receive data valid 80 SMRXD3 Ipd/O Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control. 81 SMRXD2 Ipd/O Switch MII receive bit 2. Strap option: PD (default) = Switch MII in
full-duplex mode; PU = Switch MII in half-duplex mode. 82 SMRXD1 Ipd/O Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode. 83 SMRXD0 Ipd/O Switch MII receive bit 0; Strap option: see “Register 11[1].” 84 SCOL Ipd/O Switch MII collision detect 85 SCRS Ipd/O Switch mode carrier sense Pin Function 3.3/2.5V digital VDD for digital I/O circuitry.
Switch MII receive clock. PHY or MAC mode MII. Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/internal pull-up
Ipd = Input w/internal pull-down
Ipd/O = Input w/internal pull-down during reset, output pin otherwise
Ipu/O = Input w/internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pull-down
Otri = Output tristated M9999-120403 10 December 2003