Datasheet KS8995M (Microchip) - 3

KS8995M Micrel, Inc. Revision History
Revision Date Summary of Changes 1.00 11/05/01 Created 1.01 11/09/01 Pinout Mux1/2, DVCC-IO 2.5/3.3V, feature list, register spec 11-09 1.02 12/03/01 Editorial changes, added new register and MIB descriptions. Added paragraph describing TOS registers.
Imported functional descriptions. Formatting. 1.03 12/12/01 Incorporate changes per engineering feedback as well as updating functional descriptions and adding
new timing information. 1.04 12/13/01 Changed Rev. and For. Modes to PHY and MAC modes respectively. Added MIIM clarification in “MII
Management Interface” section. Reformatted section sequence. Added hex register addresses. Added
advertisement ability descriptions. 1.05 12/18/01 Inserted switch forwarding flow charts. 1.06 12/20/01 Added new KS8995M block diagram, editorial changes, register descriptions changes and crossreferences from functional descriptions to register and strap in options. 1.07 1/22/01 Changed FXSD pins to inputs, added new descriptions to “Configuration Interfaces” section.
Edited pin descriptions. 1.08 3/1/02 Editorial changes in “Dynamic MAC Address table and “MIB Counters.” Updated figure 2 flowchart.
Updated table 2 for MAC mode connections. Separate static MAC bit assignments for read and write.
Edited read and write examples to MAC tables and MIB counters. Changed Table 3 KS8995M signals to
“S” suffix. Changed aging description in Register 2, bit 0. Changed “Port Registers” section and listed all
port register addresses. Changed port control 11 description for bits [7:5]. Changed MIB counter
descriptions. 1.09 5/17/02 Changed MII setting in “Pin Descriptions.” Changed pu/pd descriptions for SMRXD2. “Register 18,”
changed pu/pd description for forced flow control. “Illegal Frames. ” Edited large packet sizes back in.
“Elecrical Characteristics,” Added in typical supply current numbers for 100 BaseTX and 10 BaseTX
operation. “Register 18,” Added in note for illegal half-duplex, force flow control. “Pin Description,” Added
extra X1 clock input description. “Elecrical Characteristics,” Updated to chip only current numbers.
Added SPI Timing. Feature Highlights. 1.10 7/29/02 “Pin Description,” changed SMRXC and SMTXC to I/O. Input in MAC mode, output in PHY mode MII.
“Elecrical Characteristics,” modified current consumption to chip only numbers. “Half-Duplex Back
Pressure,” added description for no dropped packets in half-duplex mode. Added recommended
operating conditions. Added Idle mode current consumption in “Elecrical Characteristics,” added
“Selection of Isolation Transformers,” Added 3.01kΩ resistor instructions for ISET “Pin Description”
section. Changed Polarity of transmit pairs in “Pin Description.” Changed description for Register 2, bit 1,
in “Register Description” section. Added “Reset Timing” section. 1.11 12/17/02 “Register 3” changed 802.1x to 802.3x. “Register 6,” changed default column to disable flow control for
pull-down, and enable flow control for pull-up. “Register 29” and “Register 0” indicate loop back is at the
PHY. Added description to register 4 bit 2 to indicate that STPID packets from CPU to normal ports are
not allowed as 1522 byte tag packets. Fixed dynamic MAC address example errors in “Dynamic MAC
Address Table.” Changed definition of forced MDI, MDIX in section “Register 29,” “Register 30” and
“Register 0.” Added “Part Ordering Information.” Added Ambient operating temperature for KS8995MI 1.12 3/10/03 Changed pin 120 description to NC. Changed SPIQ pin description to Otri. Changed logo. Changed
contact information. 1.13 7/5/06 Add a note for VLAN table write, improve the timing diagram of MAC mode and PHY mode for MII
interface, change VDDIO support 3.3V only, update pin description for PCRS, PCOL, and so on. July 2006 3 M9999-070506