Datasheet KSZ8863MLL, KSZ8863FLL, KSZ8863RLL (Microchip) - 9

KSZ8863MLL/FLL/RLL TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Type Description Number Name Note 2-1 Port 2 LED Indicators:
Default: Speed (refer to register 195 bit [5:4])
Strap option:
Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit [5:4])
Strap option:
Serial bus configuration Serial bus configuration pins to select mode of access to KSZ8863MLL/ FLL/RLL internal registers.
[P2LED1, P2LED0] = [0, 0] — I2C Master (EEPROM) mode
45 P2LED1 Ipu/O (If EEPROM is not detected, the KSZ8863MLL/FLL/RLL is configured with the default values of its internal registers and the values of its strap-in pins.)
Interface Signals Type Description
SPIQ O Not used (tri-stated) SCL_MDC O I2C clock SDA_MDIO I/O I2C data I/O SPISN I Not used
[P2LED1, P2LED0] = [0, 1] — I2C Slave mode
The external I2C Master drives the SCL_MDC clock. The KSZ8863MLL/FLL/RLL device addresses are: 1011_1111 <read> 1011_1110 <write>
Interface Signals Type Description
SPIQ O Not used (tri-stated) SCL_MDC I I2C clock SDA_MDIO I/O I2C data I/O SPISN I Not used
[P2LED1, P2LED0] = [1, 0] — SPI Slave mode
46 P2LED0 Ipu/O
Interface Signals Type Description
SPIQ O SPI data out SCL_MDC I SPI clock SDA_MDIO I SPI data in SPISN I SPI chip select
[P2LED1, P2LED0] = [1, 1] – SMI/MIIM mode
In SMI mode, KSZ8863MLL/FLL/RLL provides access to all its internal 8- bit registers through its SCL_MDC and SDA_MDIO pins. In MIIM mode, KSZ8863MLL/FLL/RLL provides access to its 16-bit MIIM registers through its SDC_MDC and SDA_MDIO pins. 47 RSTN Ipu Hardware reset pin (active-low) MLL/RLL: No connection or connect to analog ground by 1 kΩ pull-down 48 FXSD1 I resistor. FLL: Fiber signal detect  2017 Microchip Technology Inc. DS00002335B-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Timing 7.7 Auto-Negotiation Timing 7.8 MDC/MDIO Timing 7.9 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service