Datasheet KSZ8794CNX (Microchip) - 7
| Fabricante | Microchip |
| Descripción | Integrated 4-Port 10/100 Managed Ethernet Switch with Gigabit RGMII/MII/RMII Interface |
| Páginas / Página | 124 / 7 — KSZ8794CNX. TABLE 2-1:. SIGNALS - KSZ8794CNX. Pin. Type. Port. … |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
KSZ8794CNX. TABLE 2-1:. SIGNALS - KSZ8794CNX. Pin. Type. Port. Description. Number. Name. Note 2-1. Note:
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KSZ8794CNX TABLE 2-1: SIGNALS - KSZ8794CNX Pin Pin Type Port Description Number Name Note 2-1
1 VDD12A P — 1.2V Core Power 2 VDDAT P — 3.3V or 2.5V Analog Power. 3 GNDA GND — Analog Ground. 4 RXP1 I 1 Port 1 Physical Receive Signal + (Differential). 5 RXM1 I 1 Port 1 Physical Receive Signal - (Differential). 6 TXP1 O 1 Port 1 Physical Transmit Signal + (Differential). 7 TXM1 O 1 Port 1 Physical Transmit Signal - (Differential). 8 RXP2 I 2 Port 2 Physical Receive Signal + (Differential). 9 RXM2 I 2 Port 2 Physical Receive Signal - (Differential). 10 TXP2 O 2 Port 2 Physical Transmit Signal + (Differential). 11 TXM2 O 2 Port 2 Physical Transmit Signal - (Differential). 12 VDDAT P — 3.3V or 2.5V Analog Power. 13 RXP3 I 3 Port 3 Physical Receive Signal + (Differential). 14 RXM3 I 3 Port 3 Physical Receive Signal - (Differential). 15 TXP3 O 3 Port 3 Physical Transmit Signal + (Differential). 16 TXM3 O 3 Port 3 Physical Transmit Signal – (Differential). 17 GNDA GND — Analog Ground. 18 INTR_N Opu — Interrupt: Active-Low This pin is an open-drain output pin.
Note:
an external pull-up resistor is needed on this pin when it is in use. 19 LED3_1 Ipu/O 3 Port 3 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: Switch Port 4 GMAC4 interface mode select by LED3[1:0] 00 = MII for SW4-MII 01 = RMII for SW4-RMII 10 = Reserved 11 = RGMII for SW4-RGMII (Default) 20 LED3_0 Ipu/O 3 Port 3 LED Indicator 0: See Global Register 11 bits [5:4] for details. Strap Option: See LED3_1. 21 VDD12D P — 1.2V Core Power. 22 GNDD GND — Digital Ground. 23 TXEN4/ Ipd 4 MII/RMII: Port 4 Switch transmit enable. TXD4_CTL RGMII: Transmit data control. 24 TXD4_0 Ipd 4 RGMII/MII/RMII: Port 4 Switch transmit bit [0]. 2016 Microchip Technology Inc. DS00002134A-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
KSZ8794CNX TABLE 2-1: SIGNALS - KSZ8794CNX Pin Pin Type Port Description Number Name Note 2-1
1 VDD12A P — 1.2V Core Power 2 VDDAT P — 3.3V or 2.5V Analog Power. 3 GNDA GND — Analog Ground. 4 RXP1 I 1 Port 1 Physical Receive Signal + (Differential). 5 RXM1 I 1 Port 1 Physical Receive Signal - (Differential). 6 TXP1 O 1 Port 1 Physical Transmit Signal + (Differential). 7 TXM1 O 1 Port 1 Physical Transmit Signal - (Differential). 8 RXP2 I 2 Port 2 Physical Receive Signal + (Differential). 9 RXM2 I 2 Port 2 Physical Receive Signal - (Differential). 10 TXP2 O 2 Port 2 Physical Transmit Signal + (Differential). 11 TXM2 O 2 Port 2 Physical Transmit Signal - (Differential). 12 VDDAT P — 3.3V or 2.5V Analog Power. 13 RXP3 I 3 Port 3 Physical Receive Signal + (Differential). 14 RXM3 I 3 Port 3 Physical Receive Signal - (Differential). 15 TXP3 O 3 Port 3 Physical Transmit Signal + (Differential). 16 TXM3 O 3 Port 3 Physical Transmit Signal – (Differential). 17 GNDA GND — Analog Ground. 18 INTR_N Opu — Interrupt: Active-Low This pin is an open-drain output pin.
Note:
an external pull-up resistor is needed on this pin when it is in use. 19 LED3_1 Ipu/O 3 Port 3 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: Switch Port 4 GMAC4 interface mode select by LED3[1:0] 00 = MII for SW4-MII 01 = RMII for SW4-RMII 10 = Reserved 11 = RGMII for SW4-RGMII (Default) 20 LED3_0 Ipu/O 3 Port 3 LED Indicator 0: See Global Register 11 bits [5:4] for details. Strap Option: See LED3_1. 21 VDD12D P — 1.2V Core Power. 22 GNDD GND — Digital Ground. 23 TXEN4/ Ipd 4 MII/RMII: Port 4 Switch transmit enable. TXD4_CTL RGMII: Transmit data control. 24 TXD4_0 Ipd 4 RGMII/MII/RMII: Port 4 Switch transmit bit [0]. 2016 Microchip Technology Inc. DS00002134A-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines