Datasheet AD8451 (Analog Devices) - 4

Data Sheet AD8451 SPECIFICATIONS
AVCC = +15 V, AVEE = −15 V; DVCC = +5 V; TA = 25°C, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
CURRENT SENSE INSTRUMENTATION AMPLIFIER Internal Fixed Gain 26 V/V Gain Error VISMEA = ±10 V ±0.1 % Gain Drift TA = TMIN to TMAX 3 ppm/°C Gain Nonlinearity VISMEA = ±10 V, RL = 2 kΩ 3 ppm Offset Voltage (RTI) ISREFH and ISREFL pins grounded −110 +110 µV Offset Voltage Drift TA = TMIN to TMAX 0.9 µV/°C Input Bias Current 15 30 nA Temperature Coefficient TA = TMIN to TMAX 150 pA/°C Input Offset Current 2 nA Temperature Coefficient TA = TMIN to TMAX 10 pA/°C Input Common-Mode Voltage Range VISVP − VISVN = 0 V AVEE + 2.3 AVCC − 2.4 V Over Temperature TA = TMIN to TMAX AVEE + 2.6 AVCC − 2.6 V Overvoltage Input Range AVCC − 55 AVEE + 55 V Differential Input Impedance 150 GΩ Input Common-Mode Impedance 150 GΩ Output Voltage Swing AVEE + 1.5 AVCC − 1.2 V Over Temperature TA = TMIN to TMAX AVEE + 1.7 AVCC − 1.4 V Capacitive Load Drive 1000 pF Short-Circuit Current 40 mA Reference Input Voltage Range ISREFH and ISREFL pins tied together AVEE AVCC V Reference Input Bias Current VISVP = VISVN = 0 V 5 µA Output Voltage Level Shift ISREFL pin grounded Maximum ISREFH pin connected to VREF pin 17 20 23 mV Scale Factor VISMEA/VISREFH 6.8 8 9.2 mV/V Common-Mode Rejection Ratio (CMRR) ΔVCM = 20 V 108 dB Temperature Coefficient TA = TMIN to TMAX 0.01 µV/V/°C Power Supply Rejection Ratio (PSRR) ΔVS = 20 V 108 122 dB Voltage Noise f = 1 kHz 9 nV/√Hz Voltage Noise, Peak to Peak f = 0.1 Hz to 10 Hz 0.2 µV p-p Current Noise f = 1 kHz 80 fA/√Hz Current Noise, Peak to Peak f = 0.1 Hz to 10 Hz 5 pA p-p Small Signal −3 dB Bandwidth 1.5 MHz Slew Rate ΔVISMEA = 10 V 5 V/µs VOLTAGE SENSE DIFFERENCE AMPLIFER Internal Fixed Gains 0.8 V/V Gain Error VIN = ±10 V ±0.1 % Gain Drift TA = TMIN to TMAX 3 ppm/°C Gain Nonlinearity VBVMEA = ±10 V, RL = 2 kΩ 3 ppm Offset Voltage (RTO) BVREFH and BVREFL pins grounded 500 µV Offset Voltage Drift TA = TMIN to TMAX 4 µV/°C Differential Input Voltage Range VBVN = 0 V, VBVREFL = 0 V −16 +16 V Input Common-Mode Voltage Range VBVMEA = 0 V −27 +27 V Differential Input Impedance 200 kΩ Input Common-Mode Impedance 90 kΩ Output Voltage Swing AVEE + 1.5 AVCC − 1.5 V Over Temperature TA = TMIN to TMAX AVEE + 1.7 AVCC − 1.7 V Capacitive Load Drive 1000 pF Short-Circuit Current 30 mA Rev. 0 | Page 3 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS IA CHARACTERISTICS DA CHARACTERISTICS CC AND CV LOOP FILTER AMPLIFIERS, AND VSET BUFFER VINT BUFFER REFERENCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW INSTRUMENTATION AMPLIFIER (IA) Reversing Polarity When Charging and Discharging IA Offset Option Battery Reversal and Overvoltage Protection DIFFERENCE AMPLIFIER (DA) CC AND CV LOOP FILTER AMPLIFIERS Compensation VINT Buffer MODE PIN, CHARGE AND DISCHARGE CONTROL APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION POWER SUPPLY CONNECTIONS CURRENT SENSE IA CONNECTIONS Current Sensors Optional Low-Pass Filter VOLTAGE SENSE DA CONNECTIONS Reverse Battery Conditions BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET) LOOP FILTER AMPLIFIERS CONNECTING TO A PWM CONTROLLER (VCTRL PIN) STEP-BY-STEP DESIGN EXAMPLE Step 1: Design the Switching Power Converter Step 2: Identify the Control Voltage Range of the ADP1972 Step 3: Determine the Control Voltage for the CV Loop Step 4: Determine the Control Voltage for the CC Loop and the Shunt Resistor Step 5: Choose the Control Voltage Sources Step 6: Select the Compensation Devices EVALUATION BOARD INTRODUCTION FEATURES AND TESTS EVALUATING THE AD8451 Test the Instrumentation Amplifier 20 mV Offset at IMEAS Output Test the Difference Amplifier 5 mV Offset at BVMEAS Output CC and CV Integrator Tests Loop Compensation SCHEMATIC AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE