Datasheet CA3140, CA3140A (Intersil) - 8

CA3140, CA3140A RS V+ +HV 7 LOAD LOAD 2 30V NO LOAD MT2 CA3140 6 120V 7 AC R 2 L 3 CA3140 6 4 MT R 1 3 L 4 FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES FOLLOWER +15V 7 0.1
µ
F 3 SIMULATED 10k
Ω
LOAD CA3140 6 2 100pF 2k
Ω
4 0.1
µ
F LOAD RESISTANCE (RL) = 2k
Ω
-15V LOAD CAPACITANCE (CL) = 100pF 2k
Ω
SUPPLY VOLTAGE: VS =
±
15V TA = 25oC 0.05
µ
F 10 1mV 1mV INVERTING 8 5k
Ω
10mV 10mV 6 +15V (V) 4 E G 2 7 A 0.1
µ
F T FOLLOWER 2 L SIMULATED 0 O 5k
Ω
INVERTING LOAD -2 CA3140 6 200
Ω
PUT V -4 100pF 2k
Ω
IN 3 4 -6 1mV 1mV 0.1
µ
F 4.99k
Ω
5.11k
Ω
-8 10mV 10mV -15V -10 SETTLING POINT 0.1 1.0 10 SETTLING TIME (
µ
s) D1 D2 1N914 1N914 FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS FIGURE 5. SETTLING TIME vs INPUT VOLTAGE Bandwidth and Slew Rate
The exceptionally fast settling time characteristics are largely For those cases where bandwidth reduction is desired, for due to the high combination of high gain and wide bandwidth example, broadband noise reduction, an external capacitor of the CA3140; as shown in Figure 6. connected between Terminals 1 and 8 can reduce the open
Input Circuit Considerations
loop -3dB bandwidth. The slew rate will, however, also be As mentioned previously, the amplifier inputs can be driven proportionally reduced by using this additional capacitor. below the Terminal 4 potential, but a series current limiting Thus, a 20% reduction in bandwidth by this technique will resistor is recommended to limit the maximum input terminal also reduce the slew rate by about 20%. current to less than 1mA to prevent damage to the input Figure 5 shows the typical settling time required to reach protection circuitry. 1mV or 10mV of the final value for various levels of large Moreover, some current limiting resistance should be signal inputs for the voltage follower and inverting unity gain provided between the inverting input and the output when amplifiers. 8 FN957.10 July 11, 2005