Datasheet ADIS16260, ADIS16265 (Analog Devices) - 10

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ADIS16260/ADIS16265 Data Sheet BASIC OPERATION
The ADIS16260 and ADIS16265 SPI interface supports full- The ADIS16260 and ADIS16265 require only power, ground, duplex serial communication (simultaneous transmit and and the four SPI signals to produce data and make it available receive) and uses the bit sequence shown in Figure 11. Processor to an embedded processor. Figure 9 provides a schematic for platforms typically support SPI communication with general- connecting the ADIS16260 and ADIS16265 to a SPI-compatible purpose serial ports that require some configuration in their processor and includes one of the configurable digital I/O lines. control registers. Table 6 provides a list of the most common The MSC_CTRL[2:0] bits are used to configure this line as a data settings that require attention to initialize the serial port of a ready indicator (see the Data Ready I/O Indicator section). processor for communication with the ADIS16260 and ADIS16265.
INPUT/OUTPUT LINES ARE COMPATIBLE WITH 3.3V OR 5V LOGIC LEVELS 5V Table 6. Generic Master Processor SPI Settings VDD Processor Setting Description 16 17 VCC VCC
Master The ADIS16260 and ADIS16265 operate
4 CS SS
as slaves
SCLK 1 SCLK
SCLK Rate ≤ 2.5 MHz Bit rate setting (SMPL_PRD[7:0] ≤ 0x07)
SYSTEM ADIS16260/ PROCESSOR MOSI 3 DIN ADIS16265
SPI Mode 3 Clock polarity, phase (CPOL = 1, CPHA = 1)
SPI MASTER SPI SLAVE
MSB First Mode Bit sequence
MISO 2 DOUT
16-Bit Mode Shift register/data length
IRQ 5 DIO1 GND GND
User registers govern all data collection and configuration.
18 19
9 00 Table 7 provides a memory map that includes all user registers, 6- 24 08 along with references to the bit assignment tables that follow the Figure 9. Electrical Connection Diagram generic bit assignments in Figure 10.
Table 5. Generic Master Processor Pin Names and Functions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 01
Pin Name Function
6-
UPPER BYTE LOWER BYTE
24 08 SS Slave select Figure 10. Generic Register Bit Definitions IRQ Interrupt request input MOSI Master output, slave input MISO Master input, slave output SCLK Serial clock
CS SCLK DIN R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 R/W A6 A5 DOUT DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB15 DB14 DB13
3 -01
NOTES
46
1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).
082 Figure 11. SPI Communication Bit Sequence Rev. E | Page 10 of 20 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Sensing Element Data Sampling and Processing User Interface SPI Interface User Registers Basic Operation SPI Write Commands SPI Read Commands Memory Map Processing Sensor Data Operational Controls Internal Sample Rate Sensor Bandwidth Digital Filtering Dynamic Range Calibration Global Commands Power Management Input/Output Functions General-Purpose I/O Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Assembly Bias Optimization Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide