Datasheet ADXRS450 (Analog Devices) - 5

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ADXRS450 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. RATE SENSITIVE AXIS Parameter Rating
The ADXRS450 is available in two package options. The Acceleration (Any Axis, 0.5 ms) SOIC_CAV package configuration is for applications that Unpowered 2000 g require a z-axis (yaw) rate sensing device. Powered 2000 g The vertical mount package (LCC_V) option is for applications Supply Voltage (PDD) −0.3 V to +6.0 V that require rate sensing in the axes parallel to the plane of the Output Short-Circuit Duration (Any Pin to Indefinite PCB (pitch and roll). See Figure 2 for details. Ground)
RATE
Temperature Range
AXIS Z-AXIS
Operating LCC_V Package −40°C to +125°C
+
SOIC_CAV Package −40°C to +125°C Storage
16 +
LCC_V Package −65°C to +150°C 2
RATE
00
9 AXIS
2- SOIC_CAV Package −40°C to +150°C 95
SOIC PACKAGE LCC_V PACKAGE
08 Stresses above those listed under Absolute Maximum Ratings Figure 2. Rate Signal Increases with Clockwise Rotation may cause permanent damage to the device. This is a stress The LCC_V package has terminals on two faces; however, the rating only; functional operation of the device at these or any terminals on the back side are for internal evaluation only and other conditions above those indicated in the operational should not be used in the end application. The terminals on the section of this specification is not implied. Exposure to absolute bottom of the package incorporate metallization bumps that maximum rating conditions for extended periods may affect ensure a minimum solder thickness for improved solder joint device reliability. reliability. These bumps are not present on the back side
THERMAL RESISTANCE
terminals and, therefore, poor solder joint reliability can be encountered if used in the end application. See Figure 32 in the θJA is specified for the worst-case conditions, that is, for a device Outline Dimensions section for a schematic of the LCC_V soldered in a printed circuit board (PCB) for surface-mount package. packages.
ESD CAUTION Table 3. Thermal Resistance Package Type θJA θJC Unit
16-Lead SOIC_CAV 191.5 25 °C/W 14-Lead Ceramic LCC_V 185.5 23 °C/W Rev. C | Page 4 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide