Datasheet ADXRS453 (Analog Devices) - 5

link to page 29
ADXRS453 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. RATE SENSITIVE AXIS Parameter Rating
The ADXRS453 is available in two package options. Acceleration (Any Axis, 0.5 ms) The SOIC_CAV package is for applications that require Unpowered 2000 g z-axis (yaw) rate sensing. Powered 2000 g The LCC_V (vertical mount) package is for applications Supply Voltage (PDD) −0.3 V to +6.0 V that require x-axis or y-axis (pitch or roll) rate sensing. Output Short-Circuit Duration Indefinite The package has terminals on two faces. However, the termi- (Any Pin to Ground) nals on the back are for internal evaluation only and should Operating Temperature Range not be used in the end application. The terminals on the LCC_V Package −55°C to +125°C bottom of the package incorporate metallization bumps SOIC_CAV Package −40°C to +125°C that ensure a minimum solder thickness for improved solder Storage Temperature Range joint reliability. These bumps are not present on the back LCC_V Package −65°C to +150°C terminals and, therefore, poor solder joint reliability can be SOIC_CAV Package −40°C to +150°C encountered if the back terminals are used in the end Stresses above those listed under Absolute Maximum Ratings application. For the outline dimensions of this package, see may cause permanent damage to the device. This is a stress Figure 38. rating only; functional operation of the device at these or any
RATE
other conditions above those indicated in the operational
AXIS Z-AXIS
section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
+
device reliability.
16 THERMAL RESISTANCE + RATE
02 0 θ
9 AXIS
JA is specified for the worst-case conditions, that is, for a device 55-
SOIC PACKAGE LCC_V PACKAGE
091 soldered in a printed circuit board (PCB) for surface-mount Figure 2. Rate Signal Increases with Clockwise Rotation packages.
Table 3. Thermal Resistance ESD CAUTION Package Type θJA θJC Unit
16-Lead SOIC_CAV (RG-16-1) 191.5 25 °C/W 14-Lead Ceramic LCC_V (EY-14-1) 185.5 23 °C/W Rev. B | Page 4 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide