Datasheet ADXRS810 (Analog Devices) - 10

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Data Sheet ADXRS810 THEORY OF OPERATION
The ADXRS810 operates on the principle of a resonator gyro.
CONTINUOUS SELF-TEST
Figure 12 presents a simplified illustration of one of four The ADXRS810 gyroscope uses a complete electromechanical polysilicon sensing structures. Each sensing structure contains self-test. An electrostatic force is applied to the gyroscope a dither frame that is electrostatically driven to resonance. This frame, resulting in a deflection of the capacitive sense fingers. produces the necessary velocity element to produce a Coriolis This deflection is exactly equivalent to deflection that occurs force when experiencing angular rate. The ADXRS810 is as a result of the external rate input. The output from the beam designed to sense Z-axis (yaw) angular rate. structure is processed by the same signal chain as a true rate When the sensing structure is exposed to angular rate, the output signal, providing complete coverage of both the resulting Coriolis force is coupled into an outer sense frame, electrical and mechanical components. which contains movable fingers that are placed between fixed The electromechanical self-test is performed continuously pickoff fingers. This forms a capacitive pickoff structure that during operation at a rate higher than the output bandwidth senses Coriolis motion. The resulting signal is fed to a series of of the device. The self-test routine generates equivalent positive gain and demodulation stages that produce the electrical rate and negative rate deflections. This information can then be signal output. The quad-sensor design rejects linear and angular filtered such that there is no overal effect on the demodulated acceleration, including external g-forces and vibration. This is rate output. achieved by mechanical y coupling the four sensing structures such that external g-forces appear as common-mode signals that can be removed by the fully differential architecture implemented in the ADXRS810.
RATE SIGNAL WITH CONTINUOUS SELF-TEST SIGNAL X SELF-TEST AMPLITUDE, INTERNALLY LOW FREQUENCY RATE INFORMATION
024
Y COMPARED TO THE SPECIFICATION TABLE LIMITS
1034- 1
Z
Figure 13. Continuous Self-Test Demodulation The difference amplitude between the positive and negative self-test deflections is filtered to f0/8000 (~1.95 Hz) and con- tinuously monitored and compared to hardcoded self-test limits. If the measured amplitude exceeds these limits (listed in the Specifications table), one of two error conditions is asserted, depending on the magnitude of self-test error. For less severe self-test error magnitudes, the CST bit of the fault 023 1034- 1 register is asserted; however, the status bits (ST[1:0]) in the Figure 12. Simplified Gyro Sense Structure sensor data response remain set to 0b01 for valid sensor data. The resonator requires 22.5 V (typical) for operation. Because For more severe self-test errors, the CST bit of the fault register only 5 V is typically available in most applications, a switching is asserted, and the status bits (ST[1:0]) in the sensor data regulator is included on-chip. If an external high voltage supply response are set to 0b00 for invalid sensor data. The thresholds is available, the inductor and diode can be omitted, and this for both failure conditions are listed in the Specifications table. supply can be connected to CP5. See the Application Circuit The user can access the self-test information by issuing a read section. command to the self-test memory register (Address 0x04). See the SPI Communication Protocol—Applications section for more information about error reporting. Rev. 0 | Page 9 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuit ADXRS810 Signal Chain Timing SPI Communications Characteristics SPI Communication Protocol—Applications Device Data Latching Command/Response SPI Communication Protocol—Bit Definitions Command/Response Bit Descriptions ADXRS810 Fault Register Bit Definitions CHK Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format ADXRS810 Memory Map Memory Register Definitions 0x00 RATE1, 0x01 RATE0 0x02 TEM1, 0x03 TEM0 0x04 LOCST1, 0x05 LOCST0 0x06 HICST1, 0x07 HICST0 0x08 QUAD1, 0x09 QUAD0 0x0A FAULT1, 0x0B FAULT0 0x0C PID1, 0x0D PID0 0x0E SN3, 0x0F SN2, 0x10 SN1, 0x11 SN0 Suggested PCB Layout Solder Profile Package Marking Codes Outline Dimensions Ordering Guide Automotive Products