Datasheet ADIS16470 (Analog Devices) - 6

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Data Sheet ADIS16470 TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2. Normal Mode Burst Read Parameter Description Min1 Typ Max Min1, 2 Typ Max Unit
fSCLK Serial clock 0.1 2.0 0.1 1.0 MHz tSTALL Stall period3 between data 16 N/A µs tREADRATE Read rate 24 µs t Chip select to SCLK edge 200 200 ns CS tDAV DOUT valid after SCLK edge 25 25 ns tDSU DIN setup time before SCLK rising edge 25 25 ns tDHD DIN hold time after SCLK rising edge 50 50 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fal times 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 0 0 ns t1 Input sync positive pulse width Pulse sync mode, MSC_CTRL = 101 (binary, see Table 101) 5 5 µs tSTDR Input sync to data ready valid transition Direct sync mode, MSC_CTRL = 001 (binary, see Table 101) 507 507 µs Pulse sync mode, MSC_CTRL = 101 (binary, see Table 101) 256 256 µs tNV Data invalid time 20 20 µs t2 Input sync period 500 500 µs 1 Guaranteed by design and characterization, but not tested in production. 2 N/A means not applicable. 3 When using the burst read mode, the stall period is not applicable.
Timing Diagrams tSCLKR tSCLKF CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV tDR DOUT MSB D14 D13 D12 D11 D10 D2 D1 LSB tDSU tDHD tDF DIN R/W A6 A5 A4 A3 A2 DC2 DC1 LSB
002 15343- Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS SCLK
003 15343- Figure 3. Stall Time and Data Rate Rev. A | Page 5 of 34 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INTRODUCTION INERTIAL SENSOR SIGNAL CHAIN Gyroscope Data Sampling Accelerometer Data Sampling External Clock Options Inertial Sensor Calibration Bartlett Window FIR Filter Averaging/Decimating Filter REGISTER STRUCTURE SERIAL PERIPHERAL INTERFACE (SPI) DATA READY (DR) READING SENSOR DATA Burst Read Function DEVICE CONFIGURATION Memory Structure USER REGISTER MEMORY MAP USER REGISTER DEFINTIONS Status/Error Flag Indicators (DIAG_STAT) GYROSCOPE DATA Gyroscope Data Formatting X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT) Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT) Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT) Acceleration Data Accelerometer Resolution X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT) Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT) Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT) Internal Temperature (TEMP_OUT) Time Stamp (TIME_STAMP) Data Update Counter (DATA_CNTR) DELTA ANGLES X-Axis Delta Angle (X_DELTANG_LOW and X_DELTANG_OUT) Y-Axis Delta Angle (Y_DELTANG_LOW and Y_DELTANG_OUT) Z-Axis Delta Angle (Z_DELTANG_LOW and Z_DELTANG_OUT) Delta Angle Resolution DELTA VELOCITY X-Axis Delta Velocity (X_DELTVEL_LOW and X_DELTVEL_OUT) Y-Axis Delta Velocity (Y_DELTVEL_LOW and Y_DELTVEL_OUT) Z-Axis Delta Velocity (Z_DELTVEL_LOW and Z_DELTVEL_OUT) Delta Velocity Resolution CALIBRATION Calibration, Gyroscope Bias (XG_BIAS_LOW and XG_BIAS_HIGH) Calibration, Gyroscope Bias (YG_BIAS_LOW and YG_BIAS_HIGH) Calibration, Gyroscope Bias (ZG_BIAS_LOW and ZG_BIAS_HIGH) Calibration, Accelerometer Bias (XA_BIAS_LOW and XA_BIAS_HIGH) Calibration, Accelerometer Bias (YA_BIAS_LOW and YA_BIAS_HIGH) Calibration, Accelerometer Bias (ZA_BIAS_LOW and ZA_BIAS_HIGH) Filter Control Register (FILT_CTRL) Miscellaneous Control Register (MSC_CTRL) Point of Percussion Linear Acceleration Effect on Gyroscope Bias Internal Clock Mode Output Sync Mode Direct Sync Mode Pulse Sync Mode Scaled Sync Mode Decimation Filter (DEC_RATE) Data Update Rate in External Sync Modes Continuous Bias Estimation (NULL_CNFG) Global Commands (GLOB_CMD) Software Reset Flash Memory Test Flash Memory Update Self Test Factory Calibration Restore Bias Correction Update Firmware Revision (FIRM_REV) Firmware Revision Day and Month (FIRM_DM) Firmware Revision Year (FIRM_Y) Product Identification (PROD_ID) Serial Number (SERIAL_NUM) Scratch Registers (USER_SCR_1 to USER_SER_3) Flash Memory Endurance Counter (FLSHCNT_LOW and FLSHCNT_HIGH) APPLICATIONS INFORMATION ASSEMBLY AND HANDLING TIPS Package Attributes Assembly Tips PCB Layout Suggestions Underfill Process Validation and Control POWER SUPPLY CONSIDERATIONS EVALUATION TOOLS Breakout Board PC-Based Evaluation, EVAL-ADIS2 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE