Datasheet ICM7555, ICM7556 (Intersil) - 6

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VDD tOUTPUT = -ln (1/3) RAC = 1.1RAC RA VDD 1 8 RA 1 8 2 7 DISCHARGE TRIGGER 2 7 OUTPUT 3 6 ICM7555 THRESHOLD RB OUTPUT 3 6 V 4 5 DD CONTROL RESET 4 5 VOLTAGE OPTIONAL C OPTIONAL C CAPACITOR CAPACITOR VDD
≤
18V
FIGURE 5. ALTERNATE ASTABLE CONFIGURATION FIGURE 6. MONOSTABLE OPERATION OUTPUT DRIVE CAPABILITY CONTROL VOLTAGE The output driver consists of a CMOS inverter capable of The Control Voltage terminal permits the two trip voltages for driving most logic families including CMOS and TTL. As such, if the Threshold and Trigger internal comparators to be driving CMOS, the output swing at all supply voltages will equal controlled. This provides the possibility of oscillation frequency the supply voltage. At a supply voltage of 4.5V or more, the modulation in the astable mode or even inhibition of ICM7555 and ICM7556 will drive at least two standard TTL oscillation, depending on the applied voltage. In the loads. monostable mode, delay times can be changed by varying the applied voltage to the Control Voltage pin. ASTABLE OPERATION RESET The circuit can be connected to trigger itself and free run as a multivibrator, see Figure 4. The output swings from rail-to-rail, The Reset terminal is designed to have essentially the same and is a true 50% duty cycle square wave. Trip points and trip voltage as the standard bipolar 555/556, i.e., 0.6V to 0.7V. output swings are symmetrical. Less than a 1% frequency At all supply voltages it represents an extremely high input variation is observed over a voltage range of +5V to +15V. impedance. The mode of operation of the Reset function is, however, much improved over the standard bipolar 1 SE/NE 555/556 in that it controls only the internal flip-flop, f = --------- 1.4 RC (EQ. 1) which in turn controls simultaneously the state of the Output The timer can also be connected as shown in Figure 5. In this and Discharge pins. This avoids the multiple threshold circuit, the frequency is as shown by Equation 2: problems sometimes encountered with slow falling edges in the bipolar devices. f = 1.44  R (EQ. 2) A + 2RBC The duty cycle is controlled by the values of RA and RB, by Equation 3: D = R (EQ. 3) A + RB  RA + 2RB MONOSTABLE OPERATION In this mode of operation, the timer functions as a one-shot (see Figure 6). Initially the external capacitor (C) is held discharged by a transistor inside the timer. Upon application of a negative Trigger pulse to pin 2, the internal flip-flop is set, which releases the short-circuit across the external capacitor and drives the Output high. The voltage across the capacitor now increases exponentially with a time constant t = RAC. When the voltage across the capacitor equals 2/3 V+, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly and also drives the OUTPUT to its low state. Trigger must return to a high state before the OUTPUT can return to a low state. FN2867 Rev 1.00 Page 6 of 13 June 28, 2016