Datasheet AD652 (Analog Devices) - 8

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AD652 CLOCK IN RIN COMPARATOR CINT V D FLOP LATCH IN CK G ONE Q SHOT AND D Q D Q INTEGRATOR COS 5V H L 1mA –VS INTEGRATOR OUTPUT THRESHOLD CLOCK COMPARATOR OUT AND OUT D FLOP OUT LATCH OUT FREQ t OUT OS tOS
00798-004 Figure 4. Block Diagram and System Waveforms Figure 4 shows that the period between output pulses is
INTEGRATOR
constrained to be an exact multiple of the clock period.
OUT
Consider an input current of exactly one quarter the value of
THRESHOLD
the reference current. In order to achieve a charge balance, the output frequency equals the clock frequency divided by four: one clock period for reset and three clock periods of integrate. 005 This is shown in Figure 5. If the input current is increased by a
CLOCK
00798- very small amount, the output frequency should also increase Figure 5. Integrator Output for IIN = 250 µA by a very small amount. Initially, however, no output change is observed for a very small increase in the input current. The Because of this, it is very difficult to observe the waveform on output frequency continues to run at one quarter of the clock, an oscilloscope. During all of this time, the signal at the output delivering an average of 250 µA to the summing junction. Since of the integrator is a sawtooth wave with an envelope that is also the input current is slightly larger than this, charge accumulates a sawtooth. See Figure 6. in the integrator and the sawtooth signal starts to drift down- ward. As the integrator sawtooth drifts down, the comparator threshold is crossed earlier and earlier in each successive cycle,
200
µ
s/BOX
until finally, a whole cycle is lost. When the cycle is lost, the integrate phase lasts for two periods of the clock instead of the
CINT
usual three periods. Thus, among a long string of divide-by- fours, an occasional divide-by-three occurs; the average of the
100
µ
s/BOX
output frequency is very close to one quarter of the clock, but the instantaneous frequency can be very different.
FREQ OUT 10
µ
s/BOX CLOCK IN 10
µ
s/BOX
00798-006 Figure 6. Integrator Output for IIN Slightly Greater than 250 µs Rev. C | Page 7 of 28 Document Outline FEATURES PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION DEFINITIONS OF SPECIFICATIONS THEORY OF OPERATION OVERRANGE SVFC CONNECTION FOR DUAL SUPPLY, POSITIVE INPUT VOLTAGES SVFC CONNECTIONS FOR NEGATIVE INPUT VOLTAGES SVFC CONNECTION FOR BIPOLAR INPUT VOLTAGES PLCC CONNECTIONS GAIN AND OFFSET CALIBRATION GAIN PERFORMANCE REFERENCE NOISE DIGITAL INTERFACING CONSIDERATIONS COMPONENT SELECTION DIGITAL GROUND SINGLE-SUPPLY OPERATION FREQUENCY-TO-VOLTAGE CONVERTER DECOUPLING AND GROUNDING FREQUENCY OUTPUT MULTIPLIER SINGLE-LINE MULTIPLEXED DATA TRANSMISSION Multiplexer Transmitter SVFC Demultiplexer Analog Signal Reconstruction ISOLATED FRONT END A-TO-D CONVERSION DELTA MODULATOR BRIDGE TRANSDUCER INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE