Datasheet ADIS16209 (Analog Devices) - 5

ADIS16209 Data Sheet Parameter Conditions Min Typ Max Unit
LOGIC INPUTS Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V Logic 1 Input High Current, IINH VIH = 3.3 V ±0.2 ±10 µA Logic 0 Input Low Current, IINL VIL = 0 V All Except RST −40 −60 μA RST3 −1 mA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS Output High Voltage, VOH ISOURCE = 1.6 mA 2.4 V Output Low Voltage, VOL ISINK = 1.6 mA 0.4 V SLEEP TIMER Timeout Period4 0.5 128 Seconds START-UP TIME5 Time until data is available Power-On Fast mode, SMPL_PRD ≤ 0x07 150 ms Normal mode, SMPL_PRD ≥ 0x08 190 ms Reset Recovery Fast mode, SMPL_PRD ≤ 0x07 30 ms Normal mode, SMPL_PRD ≥ 0x08 70 ms Sleep Mode Recovery 2.5 ms FLASH MEMORY Endurance6 20,000 Cycles Data Retention7 TJ = 85°C 20 Years CONVERSION RATE SETTING 1.04 2731 SPS POWER SUPPLY Operating Voltage Range 3.0 3.3 3.6 V Power Supply Current Normal mode, SMPL_PRD ≥ 0x08 11 14 mA Fast mode, SMPL_PRD ≤ 0x07 36 42 mA Sleep mode, −40°C to +85°C 140 350 µA 1 Guaranteed by iMEMS® packaged part testing, design, and/or characterization. 2 Self-test response changes as the square of VDD. 3 The RST pin has an internal pull-up. 4 Guaranteed by design. 5 The times presented in this section represent the time it takes to start producing data in the output registers, after the minimum VDD reaches 3.0 V. They do not represent the settling time of the internal filters. Note that for the default SENS_AVG and AVG_CNT settings, the typical settling time wil be ~1.46 seconds. For faster settling times, reduce the AVG_CNT and SMPL_PRD settings. Note that the trade-off associated with faster settling times wil be noise and power. 6 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 7 Retention lifetime equivalent at junction temperature (TJ) 55°C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature. Rev. F | Page 4 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RECOMMENDED PAD GEOMETRY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC OPERATION OUTPUT DATA REGISTERS Accelerometers Horizontal Incline Angle Vertical Incline Angle Internal Temperature Power Supply Auxiliary ADC OPERATION CONTROL REGISTERS Internal Sample Rate Power Management Digital Filtering Digital I/O Lines Data-Ready I/O Indicator Self-Test General-Purpose I/O Auxiliary DAC Global Commands CALIBRATION REGISTERS ALARM REGISTERS Status APPLICATIONS INFORMATION POWER SUPPLY CONSIDERATIONS Power-On-Reset Function Transient Current from VDD Ramp Rate Filter Settling ASSEMBLY INTERFACE BOARD OUTLINE DIMENSIONS ORDERING GUIDE