Datasheet ADXL346 (Analog Devices)

3-Axis, ±2 g /±4 g /±8 g /±16 g Ultralow Power Digital Accelerometer Data Sheet ADXL346 FEATURES GENERAL DESCRIPTION Ultralow power: as low as 23 μA in measurement mode and
The ADXL346 is a small, thin, ultralow power, 3-axis accelerometer
0.2 μA in standby mode at VS = 2.6 V (typical)
with high resolution (13-bit) measurement at up to ±16 g. Digital
Power consumption scales automatically with bandwidth
output data is formatted as 16-bit twos complement and is acces-
User-selectable resolution
sible through either an SPI (3- or 4-wire) or I2C digital interface.
Fixed 10-bit resolution
The ADXL346 is well suited for mobile device applications. It
Full resolution, where resolution increases with g range,
measures the static acceleration of gravity in tilt-sensing appli-
up to 13-bit resolution at ±16 g (maintaining 4 mg /LSB
cations, as well as dynamic acceleration resulting from motion
scale factor in all g ranges)
or shock. Its high resolution (4 mg/LSB) enables measurement
Embedded memory management system with FIFO
of inclination changes of less than 1.0°.
technology minimizes host processor load Single tap/double tap detection
Several special sensing functions are provided. Activity and
Activity/inactivity monitoring
inactivity sensing detect the presence or lack of motion by
Free-fall detection
comparing the acceleration on any axis with user-set thresholds.
Concurrent four- and six-position orientation detection
Tap sensing detects single and double taps in any direction. Free-
Supply and I/O voltage range: 1.7 V to 2.75 V
fall sensing detects if the device is falling. Orientation detection
SPI (3- and 4-wire) and I2C digital interfaces
is capable of concurrent four- and six-position sensing and a
Flexible interrupt modes mappable to either interrupt pin
user-selectable interrupt on orientation change for 2D or 3D
Measurement ranges selectable via serial command
applications. These functions can be mapped individually to
Bandwidth selectable via serial command
either of two interrupt output pins. An integrated memory
Wide temperature range (−40°C to +85°C)
management system with 32-level first in, first out (FIFO) buffer
10,000 g shock survival
can be used to store data to minimize host processor activity and
Pb free/RoHS compliant
lower overall system power consumption.
Small and thin: 3 mm × 3 mm × 0.95 mm LGA package
Low power modes enable intelligent motion-based power
APPLICATIONS
management with threshold sensing and active acceleration measurement at extremely low power dissipation.
Handsets Medical instrumentation
The ADXL346 is supplied in a small, thin, 3 mm × 3 mm ×
Gaming and pointing devices
0.95 mm, 16-lead, plastic package.
Industrial instrumentation Personal navigation devices Hard disk drive (HDD) protection FUNCTIONAL BLOCK DIAGRAM VS VDD I/O ADXL346 POWER MANAGEMENT CONTROL INT1 SENSE ADC AND ELECTRONICS DIGITAL INTERRUPT 3-AXIS FILTER LOGIC INT2 SENSOR SDA/SDI/SDIO 32-LEVEL SERIAL I/O FIFO SDO/ALT ADDRESS SCL/SCLK
001
GND CS
67- 081 Figure 1.
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE PACKAGE INFORMATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING POWER SAVINGS Power Modes Autosleep Mode Standby Mode SERIAL COMMUNICATIONS SPI Preventing Bus Traffic Errors I2C INTERRUPTS DATA_READY Bit SINGLE_TAP Bit DOUBLE_TAP Bit Activity Bit Inactivity Bit FREE_FALL Bit Watermark Bit Overrun Bit Orientation Bit FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO SELF-TEST REGISTER MAP REGISTER DEFINITIONS Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Improved Tap Bit Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Register 0x3A—TAP_SIGN (Read Only) xSIGN Bits xTAP Bits Register 0x3B—ORIENT_CONF (Read/Write) INT_ORIENT Bit Dead Zone Bits INT_3D Bit Divisor Bits Register 0x3C—Orient (Read Only) Vx Bits xD_ORIENT Bits APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING MECHANICAL CONSIDERATIONS FOR MOUNTING TAP DETECTION IMPROVED TAP DETECTION TAP SIGN THRESHOLD LINK MODE SLEEP MODE VS. LOW POWER MODE OFFSET CALIBRATION USING SELF-TEST ORIENTATION SENSING DATA FORMATTING OF UPPER DATA RATES NOISE PERFORMANCE OPERATION AT VOLTAGES OTHER THAN 2.6 V OFFSET PERFORMANCE AT LOWEST DATA RATES AXES OF ACCELERATION SENSITIVITY LAYOUT AND DESIGN RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE