ADIS16210Data SheetTIMING SPECIFICATIONS TA = 25°C, VDD = 3.3 V, unless otherwise noted. Table 2. ParameterDescriptionMin1TypMaxUnit fSCLK SCLK frequency 10 830 kHz tSTALL Stall period between data, between 16th and 17th SCLK 40 µs tCS Chip select to SCLK edge 48.8 ns tDAV DOUT valid after SCLK edge 100 ns tDSU DIN setup time before SCLK rising edge 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 ns tSR SCLK rise time 12.5 ns tSF SCLK fall time 12.5 ns tDF, tDR DOUT rise/fall times 5 12.5 ns tSFS CS high after SCLK edge 5 ns 1 Guaranteed by design, not tested. Timing DiagramstSRtDF, tDRCStSFtCStSFS1234561516SCLKtDAVDOUTMSBDB14DB13DB12DB11DB10DB2DB1LSBttDSUDHDDINR/WA6A5A4A3A2D2D1LSB 002 09593- Figure 2. SPI Timing and Sequence tSTALLCSSCLK 003 09593- Figure 3. DIN Bit Sequence Rev. C | Page 4 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BASIC OPERATION READING SENSOR DATA DEVICE CONFIGURATION USER REGISTER MAP SENSOR DATA OUTPUT DATA REGISTERS Accelerometers Inclinometers Internal Temperature Power Supply SIGNAL PROCESSING, BIAS CORRECTION, AND ALIGNMENT Digital Filtering Accelerometer/Inclinometer Resolution Accelerometer Bias Correction Gravity Vector Axis Definition Measurement Mode Two-Axis Mode User Reference Alignment SYSTEM TOOLS GLOBAL COMMANDS Software Reset User Register Save to Flash Memory Flash Memory Test Self Test Power-Down INPUT/OUTPUT FUNCTIONS Data Ready Indicator Alarm Indicator General-Purpose Input/Output DEVICE IDENTIFICATION STATUS/ERROR FLAGS FLASH MEMORY MANAGEMENT ALARMS SYSTEM ALARM STATIC ALARMS DYNAMIC ALARMS ALARM REPORTING APPLICATIONS INFORMATION INTERFACE BOARD MATING CONNECTOR OUTLINE DIMENSIONS ORDERING GUIDE