Datasheet ADXL343 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | 3-Axis, ±2 g/±4 g/±8 g/±16 g Digital Accelerometer |
| Páginas / Página | 37 / 3 — ADXL343. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 4/12—Revision 0: … |
| Formato / tamaño de archivo | PDF / 651 Kb |
| Idioma del documento | Inglés |
ADXL343. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 4/12—Revision 0: Initial Version
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ADXL343 Data Sheet TABLE OF CONTENTS
Features .. 1 Self-Test ... 20 Applications ... 1 Register Map ... 21 General Description ... 1 Register Definitions ... 22 Functional Block Diagram .. 1 Applications Information .. 26 Revision History ... 2 Power Supply Decoupling ... 26 Specifications ... 3 Mechanical Considerations for Mounting .. 26 Absolute Maximum Ratings .. 5 Tap Detection .. 26 Thermal Resistance .. 5 Threshold .. 27 Package Information .. 5 Link Mode ... 27 ESD Caution .. 5 Sleep Mode vs. Low Power Mode... 28 Pin Configuration and Function Descriptions ... 6 Offset Calibration ... 28 Typical Performance Characteristics ... 7 Using Self-Test .. 29 Theory of Operation .. 11 Data Formatting of Upper Data Rates ... 30 Power Sequencing .. 11 Noise Performance ... 31 Power Savings.. 12 Operation at Voltages Other Than 2.5 V .. 31 Serial Communications ... 13 Offset Performance at Lowest Data Rates ... 32 SPI ... 13 Axes of Acceleration Sensitivity ... 33 I2C ... 16 Layout and Design Recommendations ... 34 Interrupts ... 18 Outline Dimensions ... 35 FIFO ... 19 Ordering Guide .. 35
REVISION HISTORY 4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 36 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Data Formatting of Upper Data Rates Noise Performance Operation at Voltages Other Than 2.5 V Offset Performance at Lowest Data Rates Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide
ADXL343 Data Sheet TABLE OF CONTENTS
Features .. 1 Self-Test ... 20 Applications ... 1 Register Map ... 21 General Description ... 1 Register Definitions ... 22 Functional Block Diagram .. 1 Applications Information .. 26 Revision History ... 2 Power Supply Decoupling ... 26 Specifications ... 3 Mechanical Considerations for Mounting .. 26 Absolute Maximum Ratings .. 5 Tap Detection .. 26 Thermal Resistance .. 5 Threshold .. 27 Package Information .. 5 Link Mode ... 27 ESD Caution .. 5 Sleep Mode vs. Low Power Mode... 28 Pin Configuration and Function Descriptions ... 6 Offset Calibration ... 28 Typical Performance Characteristics ... 7 Using Self-Test .. 29 Theory of Operation .. 11 Data Formatting of Upper Data Rates ... 30 Power Sequencing .. 11 Noise Performance ... 31 Power Savings.. 12 Operation at Voltages Other Than 2.5 V .. 31 Serial Communications ... 13 Offset Performance at Lowest Data Rates ... 32 SPI ... 13 Axes of Acceleration Sensitivity ... 33 I2C ... 16 Layout and Design Recommendations ... 34 Interrupts ... 18 Outline Dimensions ... 35 FIFO ... 19 Ordering Guide .. 35
REVISION HISTORY 4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 36 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Data Formatting of Upper Data Rates Noise Performance Operation at Voltages Other Than 2.5 V Offset Performance at Lowest Data Rates Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide