Datasheet ADXL350 (Analog Devices) - 24

Data Sheet ADXL350 REGISTER MAP Table 17. Register Map Address Hex Dec Name Type Reset Value Description
0x00 0 DEVID R 11100101 Device ID. 0x01 to 0x01C 1 to 28 Reserved Reserved. Do not access. 0x1D 29 THRESH_TAP R/W 00000000 Tap threshold. 0x1E 30 OFSX R/W 00000000 X-axis offset. 0x1F 31 OFSY R/W 00000000 Y-axis offset. 0x20 32 OFSZ R/W 00000000 Z-axis offset. 0x21 33 DUR R/W 00000000 Tap duration. 0x22 34 Latent R/W 00000000 Tap latency. 0x23 35 Window R/W 00000000 Tap window. 0x24 36 THRESH_ACT R/W 00000000 Activity threshold. 0x25 37 THRESH_INACT R/W 00000000 Inactivity threshold. 0x26 38 TIME_INACT R/W 00000000 Inactivity time. 0x27 39 ACT_INACT_CTL R/W 00000000 Axis enable control for activity and inactivity detection. 0x28 40 THRESH_FF R/W 00000000 Free-fall threshold. 0x29 41 TIME_FF R/W 00000000 Free-fall time. 0x2A 42 TAP_AXES R/W 00000000 Axis control for tap/double tap. 0x2B 43 ACT_TAP_STATUS R 00000000 Source of tap/double tap. 0x2C 44 BW_RATE R/W 00001010 Data rate and power mode control. 0x2D 45 POWER_CTL R/W 00000000 Power-saving features control. 0x2E 46 INT_ENABLE R/W 00000000 Interrupt enable control. 0x2F 47 INT_MAP R/W 00000000 Interrupt mapping control. 0x30 48 INT_SOURCE R 00000010 Source of interrupts. 0x31 49 DATA_FORMAT R/W 00000000 Data format control. 0x32 50 DATAX0 R 00000000 X-Axis Data 0. 0x33 51 DATAX1 R 00000000 X-Axis Data 1. 0x34 52 DATAY0 R 00000000 Y-Axis Data 0. 0x35 53 DATAY1 R 00000000 Y-Axis Data 1. 0x36 54 DATAZ0 R 00000000 Z-Axis Data 0. 0x37 55 DATAZ1 R 00000000 Z-Axis Data 1. 0x38 56 FIFO_CTL R/W 00000000 FIFO control. 0x39 57 FIFO_STATUS R 00000000 FIFO status. Rev. 0 | Page 23 of 36 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide