Datasheet ADXL375 (Analog Devices) - 10

Data Sheet ADXL375 25 200 ) 20 % ( 150 A) µ TION ( A L 15 NT PU 100 PO F CURRE O Y 10 L T PP EN C SU 50 PER 5
212
0
11669-
0 2.0 2.4 2.8 3.2 3.6
215
80 85 90 95 10 15 100 105 1 1 120 125 130 135 140 145 150 155 160 165 170 175 180 SUPPLY VOLTAGE (V)
11669-
SELF-TEST RESPONSE (LSB)
Figure 16. Z-Axis Self-Test Response at 25°C, VS = 2.5 V Figure 19. Supply Current vs. Supply Voltage (VS) at 25°C
25 200 X-AXIS, DUT1 ) 20 % X-AXIS, DUT2 ( 150 Y-AXIS, DUT1 Y-AXIS, DUT2 TION Z-AXIS, DUT1 A L Z-AXIS, DUT2 15 ) g PU T ( U PO 100 F TP O 10 T OU EN C 50 5 PER
213 216
0
11669-
0
11669-
100 110 120 130 140 150 160 170 180 190 200 0 50 100 150 200 CURRENT CONSUMPTION (µA) REFERENCE ACCELERATION (g )
Figure 17. Current Consumption at 25°C, 100 Hz Output Data Rate, VS = 2.5 V Figure 20. Output Linearity over the Dynamic Range
160 1.2 140 1.0 A) X-AXIS µ 120 Y Y-AXIS N ( IT Z-AXIS IO 0.8 T 100 ITIV P S N UM E 80 S NS 0.6 D CO 60 LIZE NT A M 0.4 40 OR N CURRE 0.2 20
214 217
0
11669-
0
11669-
1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200 10 100 1000 OUTPUT DATA RATE (Hz) FREQUENCY (Hz)
Figure 18. Current Consumption vs. Output Data Rate at 25°C, Figure 21. Frequency Response 10 Parts Soldered to PCB, VS = 2.5 V Rev. B | Page 9 of 32 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Soldering Profile Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Current Consumption and Output Data Rate Power Saving Modes Low Power Mode Autosleep Mode Standby Mode FIFO Buffer Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from the FIFO Buffer Self-Test Interrupts Enabling and Disabling Interrupts Clearing Interrupts Bits in the Interrupt Registers DATA_READY Bit SINGLE_SHOCK Bit DOUBLE_SHOCK Bit Activity Bit Inactivity Bit Watermark Bit Overrun Bit Serial Communications SPI Mode Preventing Bus Traffic Errors I2C Mode Register Map Register Descriptions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_SHOCK (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable and INACT_x Enable Bits Register 0x2A—SHOCK_AXES (Read/Write) Suppress Bit SHOCK_x Enable Bits Register 0x2B—ACT_SHOCK_STATUS (Read Only) ACT_x Source and SHOCK_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit Justify Bit Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Shock Detection Threshold Detection and Bandwidth Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz Using Self-Test Axes of Acceleration Sensitivity Layout and Design Recommendations Package Information Outline Dimensions Ordering Guide