Datasheet LTC4401-1, LTC4401-2 (Analog Devices) - 9

LTC4401-1/LTC4401-2
U U W U APPLICATIO S I FOR ATIO
10 1) The additional voltage gain supplied by the RF power 0 amplifier increases the loop gain raising poles normally –10 below the 0dB axis. The extra voltage gain can vary –20 significantly over input/output power ranges, frequency, –30 power supply, temperature and manufacturer. RF power –40 amplifier gain control transfer functions are often not RFOUT (dBc) –50 available and must be generated by the user. Loop oscil- –60 lations are most likely to occur in the midpower range –70 where the external voltage gain associated with the RF –80 power amplifier typically peaks. It is useful to measure the –28 –18 –10 0 543 553 561 571 TIME (µs) oscillation or ringing frequency to determine whether it START corresponds to the expected loop bandwidth and thus is PULSE due to high gain bandwidth. START CODE ZERO DAC VOLTAGE CODE 2) Loop voltage losses supplied by the directional coupler will improve phase margin. The larger the directional coupler loss the more stable the loop will become. How- 200mV ever, larger losses reduce the RF signal to the LTC4401-X and detector performance may be degraded at low power SHDN 12µs, ALLOWS TIME FOR DAC 4401 F01 levels. (See RF Detector Characteristics.) AND AUTOZERO TO SETTLE 3) Additional poles within the loop due to filtering or the
Figure 1. LTC4401-X Ramp Timing
turn-on response of the RF power amplifier can degrade
Demo Board
the phase margin if these pole frequencies are near the effective loop bandwidth frequency. Generally loops using The LTC4401-X demo board is available upon request. The RF power amplifiers with fast turn-on times have more demo board has a 900MHz and an 1800MHz RF channel phase margin. Extra filtering below 16MHz should never controlled by the LTC4401-X. Timing signals for SHDN are be placed within the control loop, as this will only degrade generated on the board using a 13MHz crystal reference. phase margin. The PCTL power control pin is driven by a 10-bit DAC and the DAC profile can be loaded via a serial port. The serial 4) Control loop instability can also be due to open-loop port data is stored in a flash memory which is capable of issues. RF power amplifiers should first be characterized storing eight ramp profiles. The board is supplied preloaded in an open-loop configuration to ensure self oscillation is with four GSM power profiles and four DCS power profiles not present. Self-oscillation is often related to poor power covering the entire power range. External timing signals supply decoupling, ground loops, coupling due to poor can be used in place of the internal crystal controlled layout and extreme VSWR conditions. The oscillation fre- timing. A variety of RF power amplifiers as well as ramp quency is generally in the 100kHz to 10MHz range. Power generation software are available. supply related oscillation suppression requires large value ceramic decoupling capacitors placed close to the RF
LTC4401-X Control Loop Stability
power amp supply pins. The range of decoupling capacitor values is typically 1nF to 3.3µF. The LTC4401-X provides a stable control loop for several RF power amplifier models from different manufacturers 5) Poor layout techniques associated with the directional over a wide range of frequencies, output power levels and coupler area may result in high frequency signals bypass- V ing the coupler. This could result in stability problems due SWR conditions. However, there are several factors that can improve or degrade loop frequency stability. to the reduction in the coupler loss. 4401fa 9