Datasheet LTC4317 (Analog Devices) - 10

LTC4317
operaTion Table 2. Setting the Resistive Divider at XORL
which gives 0110 0010b or 0x62. If the configuration
LOWER
voltages at XORL and XORH pins are the same, they can
4-BIT OF
be tied together and connected to a single resistive divider.
TRANSLATION BYTE
Alternatively, three resistors can be used to configure
RECOMMENDED RECOMMENDED a3 a2 a1 a0 V
the XORL and XORH pins (Figure 6). Use the following
XORL/VCC RLT [kΩ] RLB [kΩ]
0 0 0 0 ≤ 0.03125 Open Short procedure to calculate the value of the three resistors: 0 0 0 1 0.09375 ±0.015 976 102 VCC 0 0 1 0 0.15625 ±0.015 976 182 RA1 V 0 0 1 1 0.21875 ±0.015 1000 280 CC XORL 0 1 0 0 0.28125 ±0.015 1000 392 LTC4317 RA2 0 1 0 1 0.34375 ±0.015 1000 523 XORH 0 1 1 0 0.40625 ±0.015 1000 681 RA3 0 1 1 1 0.46875 ±0.015 1000 887 4317 F06 1 0 0 0 0.53125 ±0.015 887 1000 1 0 0 1 0.59375 ±0.015 681 1000
Figure 6. Address Translation Byte Configuration Using Three Resistors
1 0 1 0 0.65625 ±0.015 523 1000 1 0 1 1 0.71875 ±0.015 392 1000 1 1 0 0 0.78125 ±0.015 280 1000 First choose a total resistance value RTOTAL 1 1 0 1 0.84375 ±0.015 182 976 RA3 = RTOTAL • (VXORH/VCC) 1 1 1 0 0.90625 ±0.015 102 976 R 1 1 1 1 ≥ 0.96875 Short Open A2 = (RTOTAL • VXORL/VCC) – RA3 RA1 = RTOTAL – RA3 – RA2
Table 3. Setting the Resistive Divider at XORH
Use 1% tolerance resistors for RA1, RA2 and RA3.
UPPER 3-BIT OF
Once the XORL and XORH pins are read, the LTC4317
TRANSLATION
turns on switches N1 and N2, connecting the input and
BYTE RECOMMENDED RECOMMENDED
output, and the READY pin goes high to indicate that the
a6 a5 a4 VXORH/VCC RHT [kΩ] RHB [kΩ]
LTC4317 is ready to start address translation. 0 0 0 ≤ 0.03125 Open Short 0 0 1 0.09375 ±0.015 976 102 The address translation byte can be changed during 0 1 0 0.15625 ±0.015 976 182 operation by changing the XORH and XORL voltages and 0 1 1 0.21875 ±0.015 1000 280 toggling the ENABLE pin (high-low-high). This triggers 1 0 0 0.28125 ±0.015 1000 392 the LTC4317 to re-read the XORL and XORH voltages. 1 0 1 0.34375 ±0.015 1000 523
Enable/UVLO
1 1 0 0.40625 ±0.015 1000 681 1 1 1 0.46875 ±0.015 1000 887 If the ENABLE pin is driven below VENABLE(TH) or if VCC is below the UVLO threshold, the LTC4317 shuts down. For example, if RLT = 976k, RLB = 102k, RHT = 1000k, and The internal shift register storing the address translation RHB = 280k, the lower 4 translation bits are 0001b and byte is cleared, address translation is disabled, switches the upper 3 bits are 011b. The 8-bit hexadecimal address N1, N2 and N3 are off, the READY pin is pulled low and translation byte is obtained by adding a 0 as the LSB, the quiescent current drops to 350µA. 4317fa 10 For more information www.linear.com/LTC4317 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Timing Diagram Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Applications Package Description Revision History Typical Application Related Parts