Datasheet LTC4316 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Single I2C/SMBus Address Translator |
| Páginas / Página | 16 / 9 — OPERATION Table 2. Setting the Resistive Divider at XORL. LOWER. 4-BIT … |
| Formato / tamaño de archivo | PDF / 212 Kb |
| Idioma del documento | Inglés |
OPERATION Table 2. Setting the Resistive Divider at XORL. LOWER. 4-BIT OF. TRANSLATION. BYTE. RECOMMENDED RECOMMENDED. XORL/VCC
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LTC4316
OPERATION Table 2. Setting the Resistive Divider at XORL
natively, three resistors can be used to configure the XORL
LOWER
and XORH pins (Figure 6). Use the following procedure
4-BIT OF
to calculate the value of the three resistors:
TRANSLATION BYTE RECOMMENDED RECOMMENDED
a3 a2 a1 a0 V
V
CC
XORL/VCC RLT [kΩ] RLB [kΩ]
0 0 0 0 ≤ 0.03125 Open Short VCC RHT RLT 0 0 0 1 0.09375 ±0.015 976 102 LTC4316 0 0 1 0 0.15625 ±0.015 976 182 XORH XORL 0 0 1 1 0.21875 ±0.015 1000 280 RHB RLB 0 1 0 0 0.28125 ±0.015 1000 392 4316 F05 0 1 0 1 0.34375 ±0.015 1000 523
Figure 5. Address Translation Byte Configuration Resistors
0 1 1 0 0.40625 ±0.015 1000 681 V 0 1 1 1 0.46875 ±0.015 1000 887 CC RA1 1 0 0 0 0.53125 ±0.015 887 1000 VCC XORL 1 0 0 1 0.59375 ±0.015 681 1000 LTC4316 RA2 1 0 1 0 0.65625 ±0.015 523 1000 XORH 1 0 1 1 0.71875 ±0.015 392 1000 R 1 1 0 0 0.78125 ±0.015 280 1000 A3 1 1 0 1 0.84375 ±0.015 182 976 4316 F06 1 1 1 0 0.90625 ±0.015 102 976
Figure 6. Address Translation Byte Configuration Using
1 1 1 1 ≥ 0.96875 Short Open
Three Resistors
First choose a total resistance value RTOTAL
Table 3. Setting the Resistive Divider at XORH UPPER
RA3 = RTOTAL • (VXORH/VCC)
3-BIT OF TRANSLATION
RA2 = (RTOTAL • VXORL/VCC) – RA3
BYTE RECOMMENDED RECOMMENDED
RA1 = RTOTAL – RA3 – RA2 a6 a5 a4
VXORH/VCC RHT [kΩ] RHB [kΩ]
0 0 0 ≤ 0.03125 Open Short Use 1% tolerance resistors for RA1, RA2 and RA3. 0 0 1 0.09375 ±0.015 976 102 Once the XORL and XORH pins are read, the LTC4316 0 1 0 0.15625 ±0.015 976 182 turns on switches N1 and N2, connecting the input and 0 1 1 0.21875 ±0.015 1000 280 output, and the READY pin goes high to indicate that the 1 0 0 0.28125 ±0.015 1000 392 LTC4316 is ready to start address translation. 1 0 1 0.34375 ±0.015 1000 523 The address translation byte can be changed during 1 1 0 0.40625 ±0.015 1000 681 operation by changing the XORH and XORL voltages and 1 1 1 0.46875 ±0.015 1000 887 toggling the ENABLE pin (high-low-high). This triggers the LTC4316 to re-read the XORL and XORH voltages. For example, if RLT = 976k, RLB = 102k, RHT = 1000k, and RHB = 280k, the lower 4 translation bits are 0001b and
Enable/UVLO
the upper 3 bits are 011b. The 8-bit hexadecimal address translation byte is obtained by adding a 0 as the LSB, which If the ENABLE pin is driven below VENABLE(TH) or if VCC gives 0110 0010b or 0x62. If the configuration voltages is below the UVLO threshold, the LTC4316 shuts down. at XORL and XORH pins are the same, they can be tied The internal shift register storing the address translation together and connected to a single resistive divider. Alter- byte is cleared, address translation is disabled, switches 4316fa For more information www.linear.com/LTC4316 9
OPERATION Table 2. Setting the Resistive Divider at XORL
natively, three resistors can be used to configure the XORL
LOWER
and XORH pins (Figure 6). Use the following procedure
4-BIT OF
to calculate the value of the three resistors:
TRANSLATION BYTE RECOMMENDED RECOMMENDED
a3 a2 a1 a0 V
V
CC
XORL/VCC RLT [kΩ] RLB [kΩ]
0 0 0 0 ≤ 0.03125 Open Short VCC RHT RLT 0 0 0 1 0.09375 ±0.015 976 102 LTC4316 0 0 1 0 0.15625 ±0.015 976 182 XORH XORL 0 0 1 1 0.21875 ±0.015 1000 280 RHB RLB 0 1 0 0 0.28125 ±0.015 1000 392 4316 F05 0 1 0 1 0.34375 ±0.015 1000 523
Figure 5. Address Translation Byte Configuration Resistors
0 1 1 0 0.40625 ±0.015 1000 681 V 0 1 1 1 0.46875 ±0.015 1000 887 CC RA1 1 0 0 0 0.53125 ±0.015 887 1000 VCC XORL 1 0 0 1 0.59375 ±0.015 681 1000 LTC4316 RA2 1 0 1 0 0.65625 ±0.015 523 1000 XORH 1 0 1 1 0.71875 ±0.015 392 1000 R 1 1 0 0 0.78125 ±0.015 280 1000 A3 1 1 0 1 0.84375 ±0.015 182 976 4316 F06 1 1 1 0 0.90625 ±0.015 102 976
Figure 6. Address Translation Byte Configuration Using
1 1 1 1 ≥ 0.96875 Short Open
Three Resistors
First choose a total resistance value RTOTAL
Table 3. Setting the Resistive Divider at XORH UPPER
RA3 = RTOTAL • (VXORH/VCC)
3-BIT OF TRANSLATION
RA2 = (RTOTAL • VXORL/VCC) – RA3
BYTE RECOMMENDED RECOMMENDED
RA1 = RTOTAL – RA3 – RA2 a6 a5 a4
VXORH/VCC RHT [kΩ] RHB [kΩ]
0 0 0 ≤ 0.03125 Open Short Use 1% tolerance resistors for RA1, RA2 and RA3. 0 0 1 0.09375 ±0.015 976 102 Once the XORL and XORH pins are read, the LTC4316 0 1 0 0.15625 ±0.015 976 182 turns on switches N1 and N2, connecting the input and 0 1 1 0.21875 ±0.015 1000 280 output, and the READY pin goes high to indicate that the 1 0 0 0.28125 ±0.015 1000 392 LTC4316 is ready to start address translation. 1 0 1 0.34375 ±0.015 1000 523 The address translation byte can be changed during 1 1 0 0.40625 ±0.015 1000 681 operation by changing the XORH and XORL voltages and 1 1 1 0.46875 ±0.015 1000 887 toggling the ENABLE pin (high-low-high). This triggers the LTC4316 to re-read the XORL and XORH voltages. For example, if RLT = 976k, RLB = 102k, RHT = 1000k, and RHB = 280k, the lower 4 translation bits are 0001b and
Enable/UVLO
the upper 3 bits are 011b. The 8-bit hexadecimal address translation byte is obtained by adding a 0 as the LSB, which If the ENABLE pin is driven below VENABLE(TH) or if VCC gives 0110 0010b or 0x62. If the configuration voltages is below the UVLO threshold, the LTC4316 shuts down. at XORL and XORH pins are the same, they can be tied The internal shift register storing the address translation together and connected to a single resistive divider. Alter- byte is cleared, address translation is disabled, switches 4316fa For more information www.linear.com/LTC4316 9