Datasheet LTC4309 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| Páginas / Página | 16 / 4 — The. ELECTRICAL CHARACTERISTICS. denotes the specifi cations which apply … |
| Formato / tamaño de archivo | PDF / 205 Kb |
| Idioma del documento | Inglés |
The. ELECTRICAL CHARACTERISTICS. denotes the specifi cations which apply over the full operating
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LTC4309
The ELECTRICAL CHARACTERISTICS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VTHR(HYST) SDA, SCL Logic Input Threshold Voltage (Note 3) 50 mV Hysteresis CIN Digital Input Capacitance SDAIN, (Note 3) 10 pF SDAOUT, SCLIN, SCLOUT ILEAK Input Leakage Current SDA, SCL, ACC, DISCEN Pins l ±5 μA VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, Driven SDA/SCL = 0.2V, VCC = l 0 0.4 V VCC2 = 2.7V 2.7k to VCC on SDA, SCL, Driven SDA/SCL = 0.1V, l 120 170 205 mV VCC = VCC2 = 3.3V VILMAX Buffer Input Logic Low Voltage l 1.2 V
Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer SDAOUT, SCLOUT = OV l 25 30 35 ms VOL_FAULT FAULT Output Low Voltage IFAULT = 3mA l 0.4 V IOFF_FAULT FAULT Off Leakage Current l 0.1 ±5 μA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings setup and hold times must be adjusted accordingly. Please see the may cause permanent damage to the device. Exposure to any Absolute Operation Section of the datasheet. Maximum Rating condition for extended periods may affect device
Note 5:
Measure points are 0.3 • VCC and 0.7 • VCC. reliability and lifetime.
Note 6:
All currents into pins are positive, all voltages are referenced to
Note 2:
Test performed with connection circuity active. GND, unless otherwise specifi ed.
Note 3:
Determined by design, not subject to test.
Note 7:
IPULLUPAC varies with temperature and VCC voltage as shown in the
Note 4:
For larger equivalent bus capacitance, the skew increases, and Typical Performance Characteristics section.
TIMING DIAGRAMS ENABLE and READY Timing
tPLH_READY tPHL_READY tPLH_EN tPHL_EN ENABLE CONNECT READY 4309 TD01
SDA/SCL Propagation Delays, Rise and Fall Times
tRISE tFALL tPLH tPHL tRISE tFALL SDAIN/SCLIN SDAOUT/SCLOUT 4309 TD02
Figure 1. Timing Diagrams
4309fa 4
The ELECTRICAL CHARACTERISTICS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VTHR(HYST) SDA, SCL Logic Input Threshold Voltage (Note 3) 50 mV Hysteresis CIN Digital Input Capacitance SDAIN, (Note 3) 10 pF SDAOUT, SCLIN, SCLOUT ILEAK Input Leakage Current SDA, SCL, ACC, DISCEN Pins l ±5 μA VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, Driven SDA/SCL = 0.2V, VCC = l 0 0.4 V VCC2 = 2.7V 2.7k to VCC on SDA, SCL, Driven SDA/SCL = 0.1V, l 120 170 205 mV VCC = VCC2 = 3.3V VILMAX Buffer Input Logic Low Voltage l 1.2 V
Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer SDAOUT, SCLOUT = OV l 25 30 35 ms VOL_FAULT FAULT Output Low Voltage IFAULT = 3mA l 0.4 V IOFF_FAULT FAULT Off Leakage Current l 0.1 ±5 μA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings setup and hold times must be adjusted accordingly. Please see the may cause permanent damage to the device. Exposure to any Absolute Operation Section of the datasheet. Maximum Rating condition for extended periods may affect device
Note 5:
Measure points are 0.3 • VCC and 0.7 • VCC. reliability and lifetime.
Note 6:
All currents into pins are positive, all voltages are referenced to
Note 2:
Test performed with connection circuity active. GND, unless otherwise specifi ed.
Note 3:
Determined by design, not subject to test.
Note 7:
IPULLUPAC varies with temperature and VCC voltage as shown in the
Note 4:
For larger equivalent bus capacitance, the skew increases, and Typical Performance Characteristics section.
TIMING DIAGRAMS ENABLE and READY Timing
tPLH_READY tPHL_READY tPLH_EN tPHL_EN ENABLE CONNECT READY 4309 TD01
SDA/SCL Propagation Delays, Rise and Fall Times
tRISE tFALL tPLH tPHL tRISE tFALL SDAIN/SCLIN SDAOUT/SCLOUT 4309 TD02
Figure 1. Timing Diagrams
4309fa 4