Datasheet LTC4308 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | Low Voltage, Level Shifting Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| Páginas / Página | 16 / 4 — ELECTRICAL CHARACTERISTICS. The. denotes the specifi cations which apply … |
| Formato / tamaño de archivo | PDF / 172 Kb |
| Idioma del documento | Inglés |
ELECTRICAL CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating
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LTC4308
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer SDAOUT = SCLOUT = 0V l 25 30 35 ms
Timing Characteristics
fI2C,MAX I2C Maximum Operating Frequency (Note 3) 400 600 kHz tBUF Bus Free Time Between Stop and Start Condition (Note 3) 1.3 μs tHD,STA Hold Time After (Repeated) Start Condition (Note 3) 100 ns tSU,STA Repeated Start Condition Set-Up Time (Note 3) 0 ns tSU,STO Stop Condition Set-Up Time (Note 3) 0 ns tHD,DATI Data Hold Time Input (Note 3) 0 ns tSU,DAT Data Set-Up Time (Note 3) 100 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
Determined by design, not tested in production. may cause permanent damage to the device. Exposure to any Absolute
Note 4:
Measure points are 0.3 • VCC and 0.7 • VCC. Maximum Rating condition for extended periods may affect device
Note 5:
IPULLUPAC varies with temperature and VCC voltage as shown in the reliability and lifetime. Typical Performance Characteristics section.
Note 2:
See “Propagation Delays” in the Operations section for a
Note 6:
ICC test performed with connection circuitry active. discussion of tPHL and tPLH as a function of pull-up resistance and bus
Note 7:
All currents into pins are positive; all voltages are referenced to capacitance. GND unless otherwise specifi ed.
TIMING DIAGRAMS ENABLE, CONNECT, READY Timing
tPLH_READY tPHL_READY tPLH_EN tPHL_EN ENABLE CONNECT READY 4308 TD01
Rising and Falling Propagation Delays and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT
tRISE tFALL tPLH tPHL tRISE tFALL SDAIN/SCLIN SDAOUT/SCLOUT 4308 TD02
Figure 1. Timing Diagrams
4308f 4
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer SDAOUT = SCLOUT = 0V l 25 30 35 ms
Timing Characteristics
fI2C,MAX I2C Maximum Operating Frequency (Note 3) 400 600 kHz tBUF Bus Free Time Between Stop and Start Condition (Note 3) 1.3 μs tHD,STA Hold Time After (Repeated) Start Condition (Note 3) 100 ns tSU,STA Repeated Start Condition Set-Up Time (Note 3) 0 ns tSU,STO Stop Condition Set-Up Time (Note 3) 0 ns tHD,DATI Data Hold Time Input (Note 3) 0 ns tSU,DAT Data Set-Up Time (Note 3) 100 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
Determined by design, not tested in production. may cause permanent damage to the device. Exposure to any Absolute
Note 4:
Measure points are 0.3 • VCC and 0.7 • VCC. Maximum Rating condition for extended periods may affect device
Note 5:
IPULLUPAC varies with temperature and VCC voltage as shown in the reliability and lifetime. Typical Performance Characteristics section.
Note 2:
See “Propagation Delays” in the Operations section for a
Note 6:
ICC test performed with connection circuitry active. discussion of tPHL and tPLH as a function of pull-up resistance and bus
Note 7:
All currents into pins are positive; all voltages are referenced to capacitance. GND unless otherwise specifi ed.
TIMING DIAGRAMS ENABLE, CONNECT, READY Timing
tPLH_READY tPHL_READY tPLH_EN tPHL_EN ENABLE CONNECT READY 4308 TD01
Rising and Falling Propagation Delays and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT
tRISE tFALL tPLH tPHL tRISE tFALL SDAIN/SCLIN SDAOUT/SCLOUT 4308 TD02
Figure 1. Timing Diagrams
4308f 4