Datasheet LTC4307 (Analog Devices) - 8

LTC4307
OPERATION
moment of connection, therefore minimizing the amount
Input to Output Offset Voltage
of disturbance caused by the I/O card. When a logic low voltage, VLOW1, is driven on any of the Once the LTC4307 comes out of UVLO, it monitors both LTC4307’s data or clock pins, the LTC4307 regulates the the backplane and card sides for either a stop bit or bus idle voltage on the opposite data or clock pins to a slightly condition to indicate the completion of data transactions. higher voltage, typically 60mV above VLOW1. This offset is When both sides are idle or one side has a stop bit condi- practically independent of pull-up current (see the Typical tion while the other is idle, the input-to-output connection Performance curves). circuitry is activated, joining the SDA and SCL busses on the I/O card with those on the backplane. In addition, the
Propagation Delays
precharge circuitry is deactivated and will not be reactivated During a rising edge, the rise time on each side is de- unless the VCC voltage falls below the UVLO threshold. termined by the bus pull-up resistor and the equivalent
Connection Circuitry
capacitance on the line. If the pull-up resistors are the same, a difference in rise time occurs which is directly Once the connection circuitry is activated, the functionality proportional to the difference in capacitance between of the SDAIN and SDAOUT pins is identical. A low forced the two sides. This effect is displayed in Figure 2 for on either pin at any time results in both pin voltages be- VCC = 5.5V and a 10k pull-up resistor on each side (50pF ing low. The LTC4307 is tolerant of I2C bus DC logic low on one side and 150pF on the other). Since the output voltages up to the 0.3VCC VIL I2C specifi cation. side has less capacitance than the input, it rises faster When the LTC4307 senses a rising edge on the bus, it and the effective propagation delay is negative. deactivates its pull-down devices for bus voltages as low There is a fi nite propagation delay through the connec- as 0.48V and activates its accelerators. This methodology tion circuitry for falling waveforms. Figure 3 shows the maximizes the effectiveness of the rise time accelerator falling edge waveforms for the same pull-up resistors and circuitry and maintains compatibility with the other devices equivalent capacitance conditions as used in Figure 2. in the LTC4300 bus buffer family. Care must be taken to An external N-channel MOSFET device pulls down the ensure that devices participating in clock stretching or voltage on the side with 150pF capacitance; the LTC4307 arbitration force logic low voltages below 0.48V at the pulls down the voltage on the opposite side with a delay LTC4307 inputs. of 80ns. This delay is always positive and is a function SDAIN and SDAOUT enter a logic high state only when of supply voltage, temperature and the pull-up resistors all devices on both SDAIN and SDAOUT release high. and equivalent bus capacitances on both sides of the bus. The same is true for SCLIN and SCLOUT. This important The Typical Performance Characteristics section shows feature ensures that clock stretching, clock synchroniza- propagation delay as a function of temperature and voltage tion, arbitration and the acknowledge protocol always for 10k pull-up resistors and 50pF equivalent capacitance work, regardless of how the devices in the system are on both sides of the part. Also, the tPHL vs COUT curve for tied to the LTC4307. VCC = 5.5V shows that increasing the capacitance from 50pF to 150pF results in a t Another key feature of the connection circuitry is that it PHL increase from 81ns to 91ns. Larger output capacitances translate to longer delays (up provides bidirectional buffering, keeping the backplane to 125ns). Users must quantify the difference in propaga- and card capacitances isolated. Because of this isolation, tion times for a rising edge versus a falling edge in their the waveforms on the backplane busses look slightly systems and adjust setup and hold times accordingly. different than the corresponding card bus waveforms as described here. 4307f 8