Datasheet LTC4303 (Analog Devices) - 6

FabricanteAnalog Devices
DescripciónHot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery
Páginas / Página12 / 6 — OPERATIO. Start-Up. Input to Output Offset Voltage. Bus Stuck Low …
Formato / tamaño de archivoPDF / 563 Kb
Idioma del documentoInglés

OPERATIO. Start-Up. Input to Output Offset Voltage. Bus Stuck Low Time-Out. Connection Circuitry

OPERATIO Start-Up Input to Output Offset Voltage Bus Stuck Low Time-Out Connection Circuitry

Línea de modelo para esta hoja de datos

Versión de texto del documento

LTC4303
U OPERATIO Start-Up
the waveforms on the backplane busses look slightly When the LTC4303 fi rst receives power on its V different than the corresponding card bus waveforms, as CC pin, either during power up or live insertion, it starts in an under described here. voltage lockout (UVLO) state, ignoring any activity on the
Input to Output Offset Voltage
SDA or SCL pins until VCC rises above 2.5V (typical). When a logic low voltage, V During this time, the precharge circuitry is active and LOW1, is driven on any of the LTC4303’s data or clock pins, the LTC4303 regulates the forces 1V through 200k nominal resistors to the SDA voltage on the opposite side of the part (call it V and SCL pins. Because the I/O card is being plugged LOW2) to a slightly higher voltage, as directed by the following into a live backplane, the voltage on the backplane SDA equation: and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the VLOW2 = VLOW1 + 75mV + (VCC/R) • 20Ω (typical) worst-case voltage differential these pins will see at the where R is the bus pull-up resistance in ohms. For ex- moment of connection, therefore minimizing the amount ample, if a device is forcing SDAOUT to 10mV where of disturbance caused by the I/O card. VCC = 3.3V and the pull-up resistor R on SDAIN is 10k, Once the LTC4303 comes out of UVLO, it assumes that then the voltage on SDAIN = 10mV + 75mV + (3.3/10000) SDAIN and SCLIN have been inserted into a live system • 20 = 91.6mV (typical). See the Typical Performance and that SDAOUT and SCLOUT are being powered up at Characteristics section for curves showing the offset the same time as itself. Therefore, it looks for either a stop voltage as a function of VCC and R. bit or bus idle condition on the input side to indicate the completion of a data transaction. When either one occurs,
Bus Stuck Low Time-Out
the part also verifi es that both the SDAOUT and SCLOUT When SDAOUT or SCLOUT is low, an internal timer starts. voltages are high. When all of these conditions are met, The timer is only reset when SDAOUT and SCLOUT are the input-to-output connection circuitry is activated, join- both high. If they do not go high within 30ms (typical), ing the SDA and SCL busses on the I/O card with those the connection between SDAIN and SDAOUT, and SCLIN on the backplane and READY goes high. and SCLOUT is broken. After a delay of at least 40µs the LTC4303 automatically generates up to 16 clock pulses at
Connection Circuitry
8.5kHz (typical) on SCLOUT in an attempt to unstick the Once the connection circuitry is activated, the functionality bus. When SDAOUT and SCLOUT go high, reconnection of the SDAIN and SDAOUT pins is identical. A low forced occurs when the conditions described in the “Start-Up” on either pin at any time results in both pin voltages be- section above are satisfi ed. ing low.
For proper operation, logic low input voltages
When powering up into a bus stuck low condition, the
should be no higher than 0.4V with respect to the ground
connection circuitry joining the SDA and SCL busses on
pin voltage of the LTC4303.
SDAIN and SDAOUT enter the I/O card with those on the backplane is not activated. a logic high state only when all devices on both SDAIN 30ms after UVLO, automatic clocking takes place as and SDAOUT release high. The same is true for SCLIN described above. and SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the ac-
Propagation Delays
knowledge protocol always work, regardless of how the devices in the system are tied to the LTC4303. During a rising edge, the rise-time on each side is de- termined by the bus pull-up resistor and the equivalent Another key feature of the connection circuitry is that it capacitance on the line. If the pull-up resistors are the provides bidirectional buffering, keeping the backplane same, a difference in rise-time occurs which is directly and card capacitances isolated. Because of this isolation, proportional to the difference in capacitance between 4303fb 6