Datasheet LTC4301L (Analog Devices) - 6

LTC4301L
U OPERATIO Start-Up Input-to-Output Offset Voltage
When the LTC4301L first receives power on its VCC pin, When a logic low voltage, VLOW1, is driven on any of the either during power-up or live insertion, it starts in an LTC4301L’s data or clock pins, the LTC4301L regulates undervoltage lockout (UVLO) state, ignoring any activity the voltage on the other side of the device (call it VLOW2) on the SDA or SCL pins until VCC rises above 2.5V. This is at a slightly higher voltage, as directed by the following to ensure that the part does not try to function until it has equation: enough voltage to do so. VLOW2 = VLOW1 + 75mV + (VCC/R) • 70Ω (typical) During this time, the 1V precharge circuitry is active and where R is the bus pull-up resistance in ohms. For ex- forces 1V through 200k nominal resistors to the SDAOUT ample, if a device is forcing SDAOUT to 10mV where V and SCLOUT pins. Precharging the SCLOUT and SDAOUT CC = 3.3V and the pull-up resistor R on SDAIN is 10k, then the pins to 1V minimizes the worst-case voltage differential voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 = these pins will see at the moment of connection, therefore 108mV(typical). See the Typical Performance Character- minimizing bus disturbances. istics section for curves showing the offset voltage as a Once the LTC4301L comes out of UVLO, it assumes that function of VCC and R. SDAIN and SCLIN have been inserted into a live system and that SDAOUT and SCLOUT are being powered up at
Propagation Delays
the same time as itself. Therefore, it looks for either a stop During a rising edge, the rise time on each side is deter- bit or bus idle condition on the backplane side to indicate mined by the bus pull-up resistor and the equivalent the completion of a data transaction. When either one capacitance on the line. In Figure 1, VCC = 3.3V, SDAOUT occurs, the part also verifies that both the SDAOUT and and SCLOUT are pulled-up to 3.3V with 10k resistor (20pF SCLOUT voltages are high. When all of these conditions on this side) and SDAIN and SCLIN are pulled-up to 1.2V are met, the input-to-output connection circuitry is acti- with a 2k resistor (55pF on this side). Lower pull-up vated, joining the SDA and SCL busses on the I/O card with resistor values are used on the input side to allow the those on the backplane. output side to be released sooner.
Connection Circuitry
Once the connection circuitry is activated, the functional- ity of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages OUTPUT INPUT being low. For proper operation, logic low input voltages SIDE SIDE 20pF 55pF should be no higher than 0.4V with respect to the ground pin voltage of the LTC4301L. SDAIN and SDAOUT enter a 0.5V/DIV logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretch- 4301 TA01b 1µs/DIV ing, clock synchronization, arbitration and the acknowl-
Figure 1. Input-Output Connection
edge protocol always work, regardless of how the devices in the system are tied to the LTC4301L. There is a finite high to low propagation delay through the Another key feature of the connection circuitry is that it connection circuitry for falling waveforms. Figure 2 shows provides bidirectional buffering, keeping the backplane the falling edge waveforms for the same pull-up resistors and card capacitances isolated. Because of this isolation, and equivalent capacitance conditions as used in Figure 1. the waveforms on the backplane busses look slightly An external N-channel MOSFET device pulls down the different than the corresponding card bus waveforms as voltage on the side with 55pF capacitance; LTC4301L pulls described here. down the voltage on the opposite side with a delay of 60ns. 4301lfa 6