Datasheet ATM90E26 (Microchip) - 8

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2 PIN DESCRIPTION Table-1 Pin Description Name Pin No. I/O note 1 Type Description Reset
:
Reset Pin (active low)
This pin should connect to ground through a 0.1 Reset 4 I LVTTL μF filter capacitor. In appli- cation it can also directly connect to one output pin from microcontroller (MCU).
DVDD: Digital Power Supply
DVDD 3 I Power This pin provides power supply to the digital part. It should be decoupled with a 10μF electrolytic capacitor and a 0.1μF capacitor. DGND 2 I Power
DGND: Digital Ground AVDD: Analog Power Supply
AVDD 5 I Power This pin provides power supply to the analog part. It should be decoupled with a 0.1μF capacitor.
Vref: Output Pin for Reference Voltage
Vref 13 O Analog This pin should be decoupled with a 1μF capacitor and a 1nF capacitor. AGND 6, 14 I Power
AGND: Analog Ground I1P: Positive Input for L Line Current
I1P 10
I1N: Negative Input for L Line Current
I Analog I1N 11 These pins are differential inputs for L line current. Input range is 5μVrms~25mVrms when gain is '24'.
I2P: Positive Input for N Line Current
I2P 7
I2N: Negative Input for N Line Current
I Analog I2N 8 These pins are differential inputs for N line current. Input range is 120μVrms~600mVrms when gain is '1'.
VP: Positive Input for Voltage
VP 16
VN: Negative Input for Voltage
I Analog VN 15 These pins are differential inputs for voltage. Input range is 120μVrms~600mVrms.
USEL: UART/SPI Interface Selection
High: UART interface USEL 12 I LVTTL Low: SPI interface
Note:
This pin should not change after reset.
CS: Chip Select (Active Low) of SPI
In 4-wire SPI mode, this pin must be driven from high to low for each read/ write operation, and maintain low for the entire operation. In 3-wire SPI CS 24 I LVTTL mode, this pin must be low all the time. Refer to section 4.1. In UART interface, this pin should be connected to VDD.
SCLK: Serial Clock of SPI
This pin is used as the clock for the SPI interface. Data on SDI is shifted into the chip on the rising edge of SCLK while data on SDO is shifted out of the SCLK 25 I LVTTL chip on the falling edge of SCLK. In UART interface, this pin should be connected to ground. M90E26 [DATASHEET] 8 Atmel-46002B-SE-M90E26-Datasheet_110714 Document Outline Features Application Description Block Diagram 1 Pin Assignment 2 Pin Description 3 Functional Description 3.1 Dynamic Metering Range 3.2 Startup and No-Load Power 3.3 Energy Registers 3.4 N Line Metering and Anti-Tampering 3.4.1 Metering Mode and L/N Line Current Sampling Gain Configuration 3.4.2 Anti-Tampering Mode Threshold Compare Method Special Treatment at Low Power 3.5 Measurement and Zero-Crossing 3.5.1 Measurement 3.5.2 Zero-Crossing 3.6 Calibration 3.7 Reset 4 Interface 4.1 SPI Interface 4.1.1 Four-Wire Mode Read Sequence Write Sequence 4.1.2 Three-Wire Mode 4.1.3 Timeout and Protection 4.2 UART Interface 4.2.1 Byte Level Timing 4.2.2 Write Transaction 4.2.3 Read transaction 4.2.4 Checksum 4.3 WarnOut Pin for Fatal Error Warning 4.4 Low Cost Implementation in Isolation with MCU 5 Register 5.1 Register List 5.2 Status and Special Register SoftReset Software Reset SysStatus System Status FuncEn Function Enable SagTh Voltage Sag Threshold SmallPMod Small-Power Mode LastData Last Read/Write SPI/UART Value 5.3 Metering/ Measurement Calibration and Configuration 5.3.1 Metering Calibration and Configuration Register LSB RMS/Power 16-bit LSB CalStart Calibration Start Command PLconstH High Word of PL_Constant PLconstL Low Word of PL_Constant Lgain L Line Calibration Gain Lphi L Line Calibration Angle Ngain N Line Calibration Gain Nphi N Line Calibration Angle PStartTh Active Startup Power Threshold PNolTh Active No-Load Power Threshold QStartTh Reactive Startup Power Threshold QNolTh Reactive No-Load Power Threshold MMode Metering Mode Configuration CS1 Checksum 1 5.3.2 Measurement Calibration Register AdjStart Measurement Calibration Start Command Ugain Voltage rms Gain IgainL L Line Current rms Gain IgainN N Line Current rms Gain Uoffset Voltage Offset IoffsetL L Line Current Offset IoffsetN N Line Current Offset PoffsetL L Line Active Power Offset QoffsetL L Line Reactive Power Offset PoffsetN N Line Active Power Offset QoffsetN N Line Reactive Power Offset CS2 Checksum 2 5.4 Energy Register Theory of Energy Registers APenergy Forward Active Energy ANenergy Reverse Active Energy ATenergy Absolute Active Energy RPenergy Forward (Inductive) Reactive Energy RNenergy Reverse (Capacitive) Reactive Energy RTenergy Absolute Reactive Energy EnStatus Metering Status 5.5 Measurement Register Irms L Line Current rms Urms Voltage rms Pmean L Line Mean Active Power Qmean L Line Mean Reactive Power Freq Voltage Frequency PowerF L Line Power Factor Pangle Phase Angle between Voltage and L Line Current Smean L Line Mean Apparent Power Irms2 N Line Current rms Pmean2 N Line Mean Active Power Qmean2 N Line Mean Reactive Power PowerF2 N Line Power Factor Pangle2 Phase Angle between Voltage and N Line Current Smean2 N Line Mean Apparent Power 6 Electrical Specification 6.1 Electrical Specification 6.2 SPI Interface Timing 6.3 Power On Reset Timing 6.4 Zero-Crossing Timing 6.5 Voltage Sag Timing 6.6 Pulse Output 6.7 Absolute Maximum Rating Ordering Information Packaging Drawings Revision History