Datasheet TC1320 (Microchip) - 4
| Fabricante | Microchip |
| Descripción | 8-Bit Digital-to-Analog Converter with Two-Wire Interface |
| Páginas / Página | 16 / 4 — TC1320. TC1320 ELECTRICAL SPECIFICATIONS (CONTINUED). Electrical … |
| Formato / tamaño de archivo | PDF / 211 Kb |
| Idioma del documento | Inglés |
TC1320. TC1320 ELECTRICAL SPECIFICATIONS (CONTINUED). Electrical Characteristics:. Symbol. Parameter. Min. Typ. Max. Unit
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TC1320 TC1320 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics:
VDD = 2.7V to 5.5V, -40°C TA +85°C, VREF = 1.2V unless otherwise noted.
Symbol Parameter Min Typ Max Unit Test Conditions Serial Port AC Timing
fSMB SMBus Clock Frequency 10 — 100 kHz tIDLE Bus Free Time Prior to New Transition 4.7 — — sec tH(START) START Condition Hold Time 4.0 — — sec tSU(START) START Condition Setup Time 4.7 — — sec 90% SCL to 10% SDA (for Repeated START Condition) tSU(STOP) STOP Condition Setup Time 4.0 — — sec tH-DATA Data In Hold Time 100 — — nsec tSU-DATA Data In Setup Time 100 — — nsec tLOW Low Clock Period 4.7 — — sec 10% to 10% tHIGH High Clock Period 4 — — sec 90% to 90% tF SMBus Fall Time — — 300 nsec 90% to 10% tR SMBus Rise Time — — 1000 nsec 10% to 90% t POR Power-on Reset Delay — 500 — sec VDD VPOR (Rising Edge)
Note 1:
SDA and SCL must be connected to VDD or GND.
2:
Measured at VOUT 50mV referred to GND to avoid output buffer clipping. DS21386C-page 4 2002-2012 Microchip Technology Inc.
VDD = 2.7V to 5.5V, -40°C TA +85°C, VREF = 1.2V unless otherwise noted.
Symbol Parameter Min Typ Max Unit Test Conditions Serial Port AC Timing
fSMB SMBus Clock Frequency 10 — 100 kHz tIDLE Bus Free Time Prior to New Transition 4.7 — — sec tH(START) START Condition Hold Time 4.0 — — sec tSU(START) START Condition Setup Time 4.7 — — sec 90% SCL to 10% SDA (for Repeated START Condition) tSU(STOP) STOP Condition Setup Time 4.0 — — sec tH-DATA Data In Hold Time 100 — — nsec tSU-DATA Data In Setup Time 100 — — nsec tLOW Low Clock Period 4.7 — — sec 10% to 10% tHIGH High Clock Period 4 — — sec 90% to 90% tF SMBus Fall Time — — 300 nsec 90% to 10% tR SMBus Rise Time — — 1000 nsec 10% to 90% t POR Power-on Reset Delay — 500 — sec VDD VPOR (Rising Edge)
Note 1:
SDA and SCL must be connected to VDD or GND.
2:
Measured at VOUT 50mV referred to GND to avoid output buffer clipping. DS21386C-page 4 2002-2012 Microchip Technology Inc.