Datasheet MCP47FVBXX (Microchip) - 8

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MCP47FVBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted.
DC Characteristics
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Resistor Ladder RL 100 140 180 k 1.8V  VDD  5.5V, Resistance VREF  1.0V
(7 )
Resolution N 256 Taps 8-bit No Missing Codes (# of Resistors 1024 Taps 10-bit No Missing Codes and # of Taps) (see 4096 Taps 12-bit No Missing Codes
C.1 “Resolution”
) Nominal VOUT |VOUT - VOUTMEAN| — 0.5 1.0 % 2.7V  VDD  5.5V(
2 )
Match (
12
) /VOUTMEAN — — 1.2 % 1.8V(
2
) VOUT Tempco (see VOUT/T — 15 — ppm/°C Code = Mid-scale
C.19 “V
(7Fh, 1FFh or 7FFh)
OUT Temperature
)
Coefficient”
VREF Pin Input VREF VSS — VDD V 1.8V  VDD  5.5V(
1 )
Voltage Range
Note 1
This parameter is ensured by design.
Note 2
This parameter is ensured by characterization.
Note 7
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For dual-channel devices (MCP47FVBX2), this is the effective resistance of the each resistor ladder. The resistance measurement is of the two resistor ladders measured in parallel.
Note 12
Variation of one output voltage to mean output voltage. DS20005405A-page 8  2015 Microchip Technology Inc. Document Outline 8- /10- /12-Bit Single/Dual Voltage Output Volatile Digital-to-Analog Converters with I²C™ Interface Features Package Types General Description Applications MCP47FVBX1 Device Block Diagram (Single-Channel Output) MCP47FVBX2 Device Block Diagram (Dual-Channel Output) Family Device Features 1.0 Electrical Characteristics Absolute Maximum Ratings (†) DC Characteristics DC Notes: 1.1 Timing Waveforms and Requirements FIGURE 1-1: VOUT Settling Time Waveforms. TABLE 1-1: Wiper Settling Timing 1.2 I2C Mode Timing Waveforms and Requirements FIGURE 1-2: Power-on and Brown-out Reset Waveforms. FIGURE 1-3: I2C™ Power-Down Command Timing. TABLE 1-2: RESET Timing FIGURE 1-4: I2C™ Bus Start/Stop Bits Timing Waveforms. FIGURE 1-5: I2C™ Bus Start/Stop Bits Timing Waveforms. TABLE 1-3: I2C Bus Start/Stop Bits and LAT Requirements FIGURE 1-6: I2C™ Bus Timing Waveforms. TABLE 1-4: I2C Bus Requirements (Slave Mode) TABLE 1-5: I2C Bus Requirements (Slave Mode) (Continued) Timing Table Notes: Temperature Specifications 2.0 Typical Performance Curves 3.0 Pin Descriptions TABLE 3-1: MCP47FVBX1 (Single-DAC) Pinout Description TABLE 3-2: MCP47FVBX2 (Dual-DAC) Pinout Description 3.1 Positive Power Supply Input (VDD) 3.2 Voltage Reference Pin (VREF) 3.3 Analog Output Voltage Pin (VOUT) 3.4 No Connect (NC) 3.5 Ground (VSS) 3.6 Latch Pin (LAT) 3.7 I2C - Serial Clock Pin (SCL) 3.8 I2C - Serial Data Pin (SDA) 4.0 General Description 4.1 Power-on Reset/Brown-out Reset (POR/BOR) 4.1.1 Power-on Reset 4.1.2 Brown-out Reset FIGURE 4-1: Power-on Reset Operation. 4.2 Device Memory 4.2.1 Volatile Register Memory (RAM) TABLE 4-1: Memory Map (x16) 4.2.2 Device Configuration Memory 4.2.3 Unimplemented Register Bits 4.2.4 Unimplemented (RESERVED) Locations TABLE 4-2: Factory Default POR / BOR Values 4.2.5 Device Registers Register 4-1: DAC0 and DAC1 Registers (Volatile) Register 4-2: Voltage Reference (VREF) Control Register (Address 08h) Register 4-3: Power-down Control Register (Address 09h) Register 4-4: Gain Control and System Status Register (Address 0Ah) 5.0 DAC Circuitry FIGURE 5-1: MCP47FVBXX DAC Module Block Diagram. 5.1 Resistor Ladder FIGURE 5-2: Resistor Ladder Model Block Diagram. 5.2 Voltage Reference Selection 5.2.1 Unbuffered Mode 5.2.2 Buffered Mode FIGURE 5-3: Resistor Ladder Reference Voltage Selection Block Diagram. FIGURE 5-4: Reference Voltage Selection Implementation Block Diagram. 5.2.3 Bandgap Mode 5.3 Output Buffer/VOUT Operation FIGURE 5-5: Output Driver Block Diagram. TABLE 5-1: Output Driver Gain 5.3.1 Programmable Gain 5.3.2 Output Voltage 5.3.3 Step Voltage (VS) TABLE 5-2: Theoretical Step Voltage (VS) (1) 5.3.4 Output Slew Rate FIGURE 5-6: VOUT Pin Slew Rate. 5.3.5 Driving Resistive and Capacitive Loads FIGURE 5-7: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). TABLE 5-3: DAC Input Code Vs. Calculated Analog Output (VOUT) (VDD = 5.0V) 5.4 Internal Band Gap TABLE 5-4: VOUT Using Band Gap 5.5 Latch Pin (LAT) FIGURE 5-8: LAT and DAC Interaction. FIGURE 5-9: Example Use of LAT Pin Operation. 5.6 Power-Down Operation FIGURE 5-10: VOUT Power-Down Block Diagram. TABLE 5-5: Power-down bits and Output resistive load TABLE 5-6: DAC Current Sources 5.6.1 Exiting Power-Down 5.6.2 Reset Commands 5.7 DAC Registers, Configuration Bits, and Status Bits 6.0 I2C Serial Interface Module FIGURE 6-1: Typical I2C Interface. 6.1 Overview 6.2 Interface Pins (SCL and SDA) 6.3 Communication Data Rates 6.4 POR/BOR 6.5 Device Memory Address 6.6 General Call Commands 6.7 Multi-Master Systems 6.8 Device I2C Slave Addressing FIGURE 6-2: Slave Address Bits in the I2C Control Byte. TABLE 6-1: I2C Address/Order Code 6.9 Entering High-Speed (HS) Mode 6.9.1 Slope Control 6.9.2 Pulse Gobbler FIGURE 6-3: HS Mode Sequence. 7.0 Device Commands 7.0.1 Aborting a Transmission TABLE 7-1: Device Commands - Number of Clocks 7.1 Write Command (Normal and High-Voltage) 7.1.1 Single Write to Volatile Memory FIGURE 7-1: Write Random Address Command. 7.1.2 Continuous Writes to Volatile Memory 7.1.3 The High Voltage Command (HVC) Signal FIGURE 7-2: I2C ACK / NACK Behavior (Write Command Example). FIGURE 7-3: Continuous Write Commands. 7.2 Read Command (Normal and High-Voltage) 7.2.1 Single Read 7.2.2 Continuous Reads 7.2.3 Ignoring an I2C transmission and “falling Off” the bus FIGURE 7-4: Read Command - Single Memory Address. FIGURE 7-5: Read Command - Last Memory Address Accessed. FIGURE 7-6: I2C ACK/NACK Behavior (Read Command Example). FIGURE 7-7: Continuous Read Command Of Specified Address. 7.3 General Call Commands FIGURE 7-8: General Call Formats. 7.3.1 General Call Reset 7.3.2 General Call Wake-up FIGURE 7-9: General Call Reset Command. FIGURE 7-10: General Call Wake-Up Command. 8.0 Typical Applications 8.1 Connecting to I2C BUS using Pull-Up Resistors 8.1.1 Device Connection Test FIGURE 8-1: I2C Bus Connection Test. 8.2 Power Supply Considerations FIGURE 8-2: Example Circuit. 8.3 Application Examples 8.3.1 DC Set Point or Calibration FIGURE 8-3: Example Circuit Of Set Point or Threshold Calibration. FIGURE 8-4: Single-Supply “Window” DAC. 8.4 Bipolar Operation FIGURE 8-5: Digitally-Controlled Bipolar Voltage Source Example Circuit. 8.5 Selectable Gain and Offset Bipolar Voltage Output 8.5.1 Bipolar DAC Example FIGURE 8-6: Bipolar Voltage Source with Selectable Gain and Offset. 8.6 Designing a Double-Precision DAC FIGURE 8-7: Simple Double Precision DAC using MCP47FVBX2. 8.7 Building Programmable Current Source FIGURE 8-8: Digitally-Controlled Current Source. 8.8 Serial Interface Communication Times TABLE 8-1: Serial Interface Times / Frequencies 8.9 Software I2C Interface Reset Sequence FIGURE 8-9: Software Reset Sequence Format. 8.10 Design Considerations 8.10.1 Power Supply Considerations FIGURE 8-10: Typical Microcontroller Connections. 8.10.2 Layout Considerations TABLE 8-2: Package Footprint(1) 9.0 Development Support 9.1 Development Tools 9.2 Technical Documentation TABLE 9-1: Development Tools (Note 1) TABLE 9-2: Technical Documentation FIGURE 9-1: MCP47FVBXX Evaluation Board Circuit Using TSSOP20EV. 10.0 Packaging Information 10.1 Package Marking Information Appendix A: Revision History Revision A (May 2015) Appendix B: I2C Serial Interface FIGURE B-1: Typical I2C Interface. B.1 Overview B.2 Signal Descriptions B.3 I2C Operation FIGURE B-2: Start Bit. FIGURE B-3: Data Bit. FIGURE B-4: Acknowledge Waveform. FIGURE B-5: Repeat Start Condition Waveform. FIGURE B-6: Stop Condition Receive or Transmit Mode. FIGURE B-7: Typical 8-Bit I2C Waveform Format. FIGURE B-8: I2C Data States and Bit Sequence. FIGURE B-9: I2C Slave Address Control Byte. FIGURE B-10: HS Mode Sequence. FIGURE B-11: General Call Formats. Appendix C: Terminology C.1 Resolution C.2 Least Significant Bit (LSb) EQUATION C-1: LSb Voltage Calculation C.3 Monotonic Operation FIGURE C-1: VW (VOUT). C.4 Full-Scale Error (EFS) EQUATION C-2: Full Scale Error C.5 Zero-Scale Error (EZS) EQUATION C-3: Zero Scale Error C.6 Total Unadjusted Error (ET) EQUATION C-4: Total Unadjusted Error Calculation C.7 Offset Error (EOS) FIGURE C-2: Offset Error (Zero Gain Error). C.8 Offset Error Drift (EOSD) C.9 Gain Error (EG) FIGURE C-3: Gain Error and Full-Scale Error Example. EQUATION C-5: Example Gain Error C.10 Gain-Error Drift (EGD) C.11 Integral Nonlinearity (INL) EQUATION C-6: INL Error FIGURE C-4: INL Accuracy. C.12 Differential Nonlinearity (DNL) EQUATION C-7: DNL Error FIGURE C-5: DNL Accuracy. C.13 Settling Time C.14 Major-Code Transition Glitch C.15 Digital Feed-through C.16 -3 dB Bandwidth C.17 Power-Supply Sensitivity (PSS) EQUATION C-8: PSS Calculation C.18 Power-Supply Rejection Ratio (PSRR) C.19 VOUT Temperature Coefficient C.20 Absolute Temperature Coefficient C.21 Noise Spectral Density Product Identification System Trademarks Worldwide Sales and Service