Datasheet MCP47A1 (Microchip) - 8

link to page 11 link to page 11
MCP47A1 1.1 I2C Mode Timing Waveforms and Requirements
SCL 91 93 90 92 SDA START STOP Condition Condition
FIGURE 1-1:
I2C Bus Start/Stop Bits Timing Waveforms. 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out
Note:
Refer to specification D102 (Cb) for load conditions.
FIGURE 1-2:
I2C Bus Data Timing.
TABLE 1-1: I2C BUS START/STOP BITS REQUIREMENTS I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C  TA  +125C (Extended) Operating Voltage VDD range is described in
Section 2.0 “Typical Performance Curves” Param. Symbol Characteristic Min Max Units Conditions No.
FSCL Standard Mode 0 100 kHz Cb = 400 pF, 1.8V - 5.5V Fast Mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5V D102 Cb Bus capacitive 100 kHz mode — 400 pF loading 400 kHz mode — 400 pF 90 TSU:STA START condition 100 kHz mode 4700 — ns Only relevant for repeated START condition Setup time 400 kHz mode 600 — ns 91 THD:STA START condition 100 kHz mode 4000 — ns After this period, the first clock pulse is generated Hold time 400 kHz mode 600 — ns 92 TSU:STO STOP condition 100 kHz mode 4000 — ns Setup time 400 kHz mode 600 — ns 93 THD:STO STOP condition 100 kHz mode 4000 — ns Hold time 400 kHz mode 600 — ns DS25154A-page 8  2012 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 I2C Mode Timing Waveforms and Requirements FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-2: I2C Bus Data Timing. TABLE 1-1: I2C Bus Start/Stop Bits Requirements TABLE 1-2: I2C Bus Data Requirements (Slave Mode) 2.0 Typical Performance Curves FIGURE 2-1: INL vs. Code (00h to 3Fh) and Temperature. VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V. FIGURE 2-2: INL vs. Code (00h to 3Fh) and Temperature. VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V. FIGURE 2-3: INL vs. Code (00h to 3Fh) and Temperature. VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V. FIGURE 2-4: INL vs. Code (00h to 3Fh) and Temperature. VDD = 1.8V, VREF = 1.6V, and 1.0V. FIGURE 2-5: DNL vs. Code (00h to 3Fh) and Temperature. VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V. FIGURE 2-6: DNL vs. Code (00h to 3Fh) and Temperature. VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V. FIGURE 2-7: DNL vs. Code (00h to 3Fh) and Temperature. VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V. FIGURE 2-8: DNL vs. Code (00h to 3Fh) and Temperature. VDD = 1.8V, VREF = 1.6V, and 1.0V. FIGURE 2-9: Full Scale Error (FSE) vs. Temperature. VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V. FIGURE 2-10: Full Scale Error (FSE) vs. Temperature. VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V. FIGURE 2-11: Full Scale Error (FSE) vs. Temperature. VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V. FIGURE 2-12: Full Scale Error (FSE) vs. Temperature. VDD = 1.8V, VREF = 1.6V, and 1.0V. FIGURE 2-13: Zero Scale Error (ZSE) vs. Temperature. VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V. FIGURE 2-14: Zero Scale Error (ZSE) vs. Temperature. VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V. FIGURE 2-15: Zero Scale Error (ZSE) vs. Temperature. VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V. FIGURE 2-16: Zero Scale Error (ZSE) vs. Temperature. VDD = 1.8V, VREF = 1.6V, and 1.0V. FIGURE 2-17: Total Unadjusted Error vs. Code and Temperature. VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V. FIGURE 2-18: Total Unadjusted Error vs. Code and Temperature. VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V. FIGURE 2-19: Total Unadjusted Error vs. Code and Temperature. VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V. FIGURE 2-20: Total Unadjusted Error vs. Code and Temperature. VDD = 1.8V, VREF = 1.6V, and 1.0V. FIGURE 2-21: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V. FIGURE 2-22: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V. FIGURE 2-23: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V. FIGURE 2-24: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 1.8V, VREF = 1.6V, and 1.0V. FIGURE 2-25: VIH / VIL Threshold of SDA/SCL Inputs vs. Temperature and VDD. FIGURE 2-26: VOL (SDA) vs. VDD and Temperature. FIGURE 2-27: Interface Active Current (IDD) vs. SCL Frequency (fSCL) and Temperature VDD = 1.8V, 2.7V and 5.5V, VREF = 1.0V and VDD. (no load on VOUT). FIGURE 2-28: Interface Inactive Current (STATIC) vs. Temperature and VDD. VDD = 1.8V, 2.7V and 5.5V, VREF = 1.0V and VDD. (no load on VOUT, SCL = SDA = VDD). FIGURE 2-29: VOUT vs. Resistive Load. VDD = 5.0V. FIGURE 2-30: VOUT vs. Resistive Load. VDD = 2.7V. FIGURE 2-31: VOUT vs. Source / Sink Current. VDD = 5.0V. FIGURE 2-32: VOUT vs. Source / Sink Current. VDD = 2.7V. FIGURE 2-33: VOUT Accuracy vs. VDD and Temperature. FIGURE 2-34: RVREF Resistances vs. VDD and Temperature. FIGURE 2-35: -3dB Bandwidth vs Frequency, VDD = 5.5V. FIGURE 2-36: Zero-Scale to Full-Scale Settling Time (00h to 40h), VDD = 5.0V, VREF = 5.0V, RL = 5kW, CL = 200 pF (Time scale = 2 µs / div). FIGURE 2-37: Full-Scale to Zero-Scale Settling Time (40h to 00h), VDD = 5.0V, VREF = 5.0V, RL = 5kW, CL = 200 pF (Time scale = 2 µs / div). FIGURE 2-38: Half-Scale Settling Time (10h to 30h), VDD = 5.0V, VREF = 5.0V, RL = 5kW, CL = 200 pF. (Time scale = 2 µs / div) FIGURE 2-39: Half-Scale Settling Time (30h to 10h), VDD = 5.0V, VREF = 5.0V, RL = 5kW, CL = 200 pF (Time scale = 2 µs / div). FIGURE 2-40: Digital Feedthrough (SCL signal coupling to VOUT pin); VDD = 5.0V, VREF = 5.0V, FSCL = 100 kHz, VOUT = 20h (VOUT Voltage Scale = 20 mV/div, Time scale = 2 µs / div). 2.1 Test Circuit FIGURE 2-41: -3 db Gain vs. Frequency Test. 3.0 Pin Descriptions TABLE 3-1: Pinout Description for The MCP47A1 3.1 Positive Power Supply Input (VDD) 3.2 Ground (VSS) 3.3 I2C Serial Clock (SCL) 3.4 I2C Serial Data (SDA) 3.5 Analog Output Voltage Pin (VOUT) 3.6 Voltage Reference Pin (VREF) 4.0 General Overview FIGURE 4-1: Resistor Network and Output Buffer Block Diagram. 4.1 POR/BOR Operation TABLE 4-1: Default POR Wiper Setting Selection TABLE 4-2: Device functionality at each VDD Region FIGURE 4-2: Power-up and Brown-out. 5.0 Serial Interface - I2C Module FIGURE 5-1: Typical Application I2C Bus Configurations. 5.1 I2C I/O Considerations 5.2 I2C Bit Definitions FIGURE 5-2: Start Bit. FIGURE 5-3: Data Bit. FIGURE 5-4: Acknowledge Waveform. TABLE 5-1: MCP47A1 A / A Responses FIGURE 5-5: Repeat Start Condition Waveform. FIGURE 5-6: Stop Condition Receive or Transmit Mode. FIGURE 5-7: Typical 16-bit I2C Waveform Format. FIGURE 5-8: I2C Data States and Bit Sequence. FIGURE 5-9: Slave Address Bits in the I2C Control Byte. TABLE 5-2: Device I2C Address FIGURE 5-10: General Call Formats. 5.3 Serial Commands FIGURE 5-11: I2C Single Byte Write Command Format. FIGURE 5-12: I2C Write Command Format. FIGURE 5-13: I2C Write Communication Behavior. FIGURE 5-14: I2C Read Command Format. FIGURE 5-15: I2C Read Communication Behavior. 6.0 Resistor Network 6.1 RVREF Resistance FIGURE 6-1: Resistor Network and Output Buffer Block Diagram. 6.2 RAB Resistor Ladder 6.3 Serial Buffer to Wiper Register Decode TABLE 6-1: Serial Shift Register value to Wiper Value 6.4 Resistor Variations (Voltage and Temperature) 6.5 POR Value TABLE 6-2: POR/BOR Settings 7.0 Output Buffer 7.1 Output Buffer / VOUT Operation FIGURE 7-1: Output Buffer Block Diagram. TABLE 7-1: Theoretical DAC Output Values FIGURE 7-2: Amplifier Input (VW) to Amplifier Output (VOUT) General Characteristics (VREF = VDD). FIGURE 7-3: Solving for VOUT, VREF, or DAC Register Code. 7.2 Output Slew Rate FIGURE 7-4: VOUT Pin Slew Rate. 7.3 Driving Resistive and Capacitive Loads FIGURE 7-5: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). 7.4 Output Errors TABLE 7-2: Calculation Comparison FIGURE 7-6: Output Voltage (VOUT) Error. 8.0 Applications Examples 8.1 DC Set Point or Calibration FIGURE 8-1: Set Point or Threshold Calibration. FIGURE 8-2: Example Circuit Of Set Point or Threshold Calibration. FIGURE 8-3: Single-Supply “Window” DAC. 8.2 Selectable Gain and Offset Bipolar Voltage Output FIGURE 8-4: Bipolar Voltage Source with Selectable Gain and Offset Circuit. FIGURE 8-5: Simplified Bipolar Voltage Source with Selectable Gain and Offset Circuit. 8.3 Building Programmable Current Source FIGURE 8-6: Digitally-Controlled Current Source. 8.4 Serial Interface Communication Times TABLE 8-1: Serial Interface Times / Frequencies 8.5 Software I2C Interface Reset Sequence FIGURE 8-7: Software Reset Sequence Format. 8.6 Design Considerations FIGURE 8-8: Typical Microcontroller Connections. FIGURE 8-9: Example MCP47A1 Circuit. TABLE 8-2: Package Footprint FIGURE 8-10: I2C Bus Connection Test. 9.0 Development support 9.1 Evaluation/Demonstration Boards FIGURE 9-1: SC70EV Bond Out PCB – Top Layer and Silk-Screen. 9.2 Technical Documentation TABLE 9-1: Technical Documentation 10.0 Packaging Information 10.1 Package Marking Information Appendix A: Revision History Appendix B: Terminology Product Identification System Trademarks Worldwide Sales and Service