Datasheet LTC1923 (Analog Devices) - 9

LTC1923
U U U PI FU CTIO S (GN Package/UH Package) V NDRVA, NDRVB (Pins 21, 24/Pins 19, 23):
These push-
TEC (Pin 14/Pin 12):
Output of the differential TEC voltage amplifier equal to the magnitude of the voltage across pull outputs are configured to drive the opposite low side the␣ TEC. switches in a full-bridge arrangement.
TEC– (Pin 15/Pin 13):
Inverting Input to the Differential TEC
PGND (Pin 22/Pin 20):
This is the high current ground for Voltage Amplifier. This amplifier has a fixed gain of 1 with its the IC. The external current sense resistor should be output being the voltage across the TEC with respect to referenced to this point. AGND. This input, along with TEC+, signifies whether the
VDD (Pin 23/Pins 21, 22):
Positive Supply Rail for the IC. TEC is heating or cooling the laser as indicated by the Bypass this pin to PGND and AGND with > 10µF low ESL, H/C␣ pin. ESR ceramic capacitors. The turn on voltage level for VDD
TEC+ (Pin 16/Pin 14):
Noninverting Input to the Differen- is 2.6V with 130mV of hysteresis. tial TEC Voltage Amplifier.
VREF (Pin 26/Pin 27):
This is the output of the Reference.
I
This pin should be bypassed to GND with a 1
TEC (Pin 17/Pin 15):
Output of the Differential Current µF ceramic Sense Amplifier. The voltage on this pin is equal to 10 • capacitor. The reference is able to supply a minimum of (I 10mA of current and is internally short-circuit current TEC + IRIPPLE) • RS, where ITEC is the thermoelectric cooler current, I limited. RIPPLE is the inductor ripple current and RS is the sense resistor used to sense this current. This
CT (Pin 27/Pin 28):
The triangular wave oscillator timing voltage represents only the magnitude of the current and capacitor pin is used in conjunction with RT to set the provides no direction information. Current limit occurs oscillator frequency. The equation for calculating fre- when the voltage on this pin exceeds the lesser of 1.5 quency is: times the voltage on SS, 1.5 times the voltage on ILIM or . 1.5V. When this condition is present, the pair of outputs, f = 0 75 Hz OSC which are presently conducting, are immediately turned R • C T T off. The current limit condition is cleared when the CT pin
RT (Pin 28/Pin 29):
A single resistor from RT to AGND sets reaches the next corresponding peak or valley (see Cur- the charging and discharging currents for the triangle rent Limit section). oscillator. This pin also sets the dead time between turning
CS – (Pin 18/Pin 16):
Inverting Input to the Differential one set of outputs off and turning the other set on to ensure Current Sense Amplifier. the outputs do not cross conduct. The voltage on this pin is regulated to 0.5V. For best performance, the current
CS+ (Pin 19/Pin 17):
Noninverting Input of the Differential sourced from the R Current Sense Amplifier. The amplifier has a fixed gain T pin should be limited to a maximum 150µA. Selecting R of␣ 10. T to be 10k is recommended and provides 90ns of dead time.
PDRVA, PDRVB (Pins 20, 25/Pins 18, 24):
These push- pull outputs are configured to drive the opposite high side PMOS switches in a full-bridge arrangement. 1923f 9