Datasheet PIC18F65K40, PIC18F66K40, PIC18LF65K40, PIC18LF66K40 (Microchip)
| Fabricante | Microchip |
| Descripción | 64-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology |
| Páginas / Página | 872 / 1 — PIC18(L)F65/66K40. 64-Pin, Low-Power, High-Performance Microcontrollers. … |
| Formato / tamaño de archivo | PDF / 6.6 Mb |
| Idioma del documento | Inglés |
PIC18(L)F65/66K40. 64-Pin, Low-Power, High-Performance Microcontrollers. with XLP Technology. Description. Core Features. Memory
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PIC18(L)F65/66K40 64-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology Description
These PIC18(L)F65/66K40 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications. These 64-pin devices are equipped with a 10-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They also offer a set of Core Independent Peripherals such as Complementary Waveform Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross Detect (ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system cost.
Core Features
• C Compiler Optimized RISC Architecture • Operating Speed: – DC – 64 MHz clock input over the full VDD range – 62.5 ns minimum instruction cycle • Programmable 2-Level Interrupt Priority • 31-Level Deep Hardware Stack • Four 8-Bit Timers (TMR2/4/6/7) with Hardware Limit Timer (HLT) • Five 16-Bit Timers (TMR0/1/3/5/7) • Low-Current Power-on Reset (POR) • Power-up Timer (PWRT) • Brown-out Reset (BOR) • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): – Watchdog Reset on too long or too short interval between watchdog clear events – Variable prescaler selection – Variable window size selection – All sources configurable in hardware or software
Memory
• Up to 64k bytes Program Flash Memory • Up to 3562 Bytes Data SRAM Memory • 1024 Bytes Data EEPROM © 2017 Microchip Technology Inc.
Datasheet
DS40001842D-page 1 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Operation Modes eXtreme Low-Power (XLP) Features Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features PIC18(L)F65/66K40 Family Types Pin Diagrams Pin Allocation Tables Table of Contents 1. Device Overview 1.1. New Core Features 1.1.1. XLP Technology 1.1.2. Multiple Oscillator Options and Features 1.2. Other Special Features 1.3. Details on Individual Family Members 1.4. Register and Bit naming conventions 1.4.1. Register Names 1.4.2. Bit Names 1.4.2.1. Short Bit Names 1.4.2.2. Long Bit Names 1.4.2.3. Bit Fields 1.4.3. Register and Bit Naming Exceptions 1.4.3.1. Status, Interrupt, and Mirror Bits 1.4.3.2. Legacy Peripherals 2. Guidelines for Getting Started with PIC18(L)F65/66K40 Microcontrollers 2.1. Basic Connection Requirements 2.2. Power Supply Pins 2.2.1. Decoupling Capacitors 2.2.2. Tank Capacitors 2.3. Master Clear (MCLR) Pin 2.4. ICSP™ Pins 2.5. External Oscillator Pins 2.6. Unused I/Os 3. Device Configuration 3.1. Configuration Words 3.2. Code Protection 3.2.1. Program Memory Protection 3.2.2. Data memory protection 3.3. Write Protection 3.4. User ID 3.5. Device ID and Revision ID 3.6. Register Summary - Configuration Words 3.7. Register Definitions: Configuration Words 3.7.1. CONFIG1 3.7.2. CONFIG2 3.7.3. CONFIG3 3.7.4. CONFIG4 3.7.5. CONFIG5 3.7.6. CONFIG6 3.8. Register Summary - Device and Revision 3.9. Register Definitions: Device and Revision 3.9.1. DEVICE ID 3.9.2. REVISION ID 4. Oscillator Module (with Fail-Safe Clock Monitor) 4.1. Overview 4.2. Clock Source Types 4.2.1. External Clock Sources 4.2.1.1. EC Mode 4.2.1.2. LP, XT, HS Modes 4.2.1.3. Oscillator Start-up Timer (OST) 4.2.1.4. 4x PLL 4.2.1.5. Secondary Oscillator 4.2.2. Internal Clock Sources 4.2.2.1. HFINTOSC 4.2.2.2. MFINTOSC 4.2.2.3. LFINTOSC 4.2.2.4. ADCRC (also referred to as FRC) 4.2.3. Oscillator Status and Adjustments 4.2.3.1. Internal Oscillator Frequency Adjustment 4.2.3.2. Oscillator Status and Manual Enable 4.2.3.3. HFOR and MFOR Bits 4.3. Clock Switching 4.3.1. New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits 4.3.2. PLL Input Switch 4.3.3. Clock Switch and Sleep 4.4. Fail-Safe Clock Monitor 4.4.1. Fail-Safe Detection 4.4.2. Fail-Safe Operation 4.4.3. Fail-Safe Condition Clearing 4.4.4. Reset or Wake-up from Sleep 4.5. Register Summary - OSC 4.6. Register Definitions: Oscillator Control 4.6.1. OSCCON1 4.6.2. OSCCON2 4.6.3. OSCCON3 4.6.4. OSCSTAT 4.6.5. OSCFRQ 4.6.6. OSCTUNE 4.6.7. OSCEN 5. Reference Clock Output Module 5.1. Clock Source 5.1.1. Clock Synchronization 5.2. Programmable Clock Divider 5.3. Selectable Duty Cycle 5.4. Operation in Sleep Mode 5.5. Register Summary: Reference CLK 5.6. Register Definitions: Reference Clock 5.6.1. CLKRCON 5.6.2. CLKRCLK 6. Power-Saving Operation Modes 6.1. Doze Mode 6.1.1. Doze Operation 6.1.2. Interrupts During Doze 6.2. Sleep Mode 6.2.1. Wake-up from Sleep 6.2.2. Wake-up Using Interrupts 6.2.3. Low-Power Sleep Mode 6.2.3.1. Sleep Current vs. Wake-up Time 6.2.3.2. Peripheral Usage in Sleep 6.2.4. Idle Mode 6.2.4.1. Idle and Interrupts 6.2.4.2. Idle and WWDT 6.3. Peripheral Operation in Power-Saving Modes 6.4. Register Summary - Power Savings Control 6.5. Register Definitions: Power Savings Control 6.5.1. VREGCON 6.5.2. CPUDOZE 7. (PMD) Peripheral Module Disable 7.1. Disabling a Module 7.2. Enabling a Module 7.3. Register Summary - PMD 7.4. Register Definitions: Peripheral Module Disable 7.4.1. PMD0 7.4.2. PMD1 7.4.3. PMD2 7.4.4. PMD3 7.4.5. PMD4 7.4.6. PMD5 8. Resets 8.1. Power-on Reset (POR) 8.2. Brown-out Reset (BOR) 8.2.1. BOR is Always On 8.2.2. BOR is OFF in Sleep 8.2.3. BOR Controlled by Software 8.2.4. BOR and Bulk Erase 8.3. Low-Power Brown-out Reset (LPBOR) 8.3.1. Enabling LPBOR 8.3.1.1. LPBOR Module Output 8.4. MCLR 8.4.1. MCLR Enabled 8.4.2. MCLR Disabled 8.5. Windowed Watchdog Timer (WWDT) Reset 8.6. RESET Instruction 8.7. Stack Overflow/Underflow Reset 8.8. Programming Mode Exit 8.9. Power-up Timer (PWRT) 8.10. Start-up Sequence 8.11. Determining the Cause of a Reset 8.12. Power Control (PCON0) Register 8.13. Register Summary - BOR Control and Power Control 8.14. Register Definitions: Power Control 8.14.1. BORCON 8.14.2. PCON0 9. (WWDT) Windowed Watchdog Timer 9.1. Independent Clock Source 9.2. WWDT Operating Modes 9.2.1. WWDT Is Always On 9.2.2. WWDT Is Off in Sleep 9.2.3. WWDT Controlled by Software 9.3. Time-out Period 9.4. Watchdog Window 9.5. Clearing the WWDT 9.5.1. CLRWDT Considerations (Windowed Mode) 9.6. Operation During Sleep 9.7. Register Summary - WDT Control 9.8. Register Definitions: Windowed Watchdog Timer Control 9.8.1. WDTCON0 9.8.2. WDTCON1 9.8.3. WDTPS 9.8.4. WDTTMR 10. Memory Organization 10.1. Program Memory Organization 10.1.1. Program Counter 10.1.2. Return Address Stack 10.1.2.1. Top-of-Stack Access 10.1.2.2. Return Stack Pointer 10.1.2.3. Stack Overflow and Underflow Resets 10.1.2.4. PUSH and POP Instructions 10.1.2.5. Fast Register Stack 10.1.3. Look-up Tables in Program Memory 10.1.3.1. Computed GOTO 10.1.3.2. Table Reads and Table Writes 10.2. PIC18 Instruction Cycle 10.2.1. Clocking Scheme 10.2.2. Instruction Flow/Pipelining 10.2.3. Instructions in Program Memory 10.2.4. Two-Word Instructions 10.3. Data Memory Organization 10.3.1. Bank Select Register 10.3.2. Access Bank 10.3.3. General Purpose Register File 10.3.4. Special Function Registers 10.3.5. Status Register 10.4. Data Addressing Modes 10.4.1. Inherent and Literal Addressing 10.4.2. Direct Addressing 10.4.3. Indirect Addressing 10.4.3.1. FSR Registers and the INDF Operand 10.4.3.2. FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 10.4.3.3. Operations by FSRs on FSRs 10.5. Data Memory and the Extended Instruction Set 10.5.1. Indexed Addressing with Literal Offset 10.5.2. Instructions Affected by Indexed Literal Offset Mode 10.5.3. Mapping the Access Bank in Indexed Literal Offset Mode 10.6. PIC18 Instruction Execution and the Extended Instruction Set 10.7. Register Summary: Memory and Status 10.8. Register Definitions: Memory and Status 10.8.1. PCL 10.8.2. PCLAT 10.8.3. TOS 10.8.4. STKPTR 10.8.5. STATUS 10.8.6. WREG 10.8.7. INDF 10.8.8. POSTDEC 10.8.9. POSTINC 10.8.10. PREINC 10.8.11. PLUSW 10.8.12. FSR 10.8.13. BSR 11. (NVM) Nonvolatile Memory Control 11.1. Program Flash Memory 11.1.1. Table Pointer Operations 11.1.1.1. Table Pointer Register 11.1.1.2. Table Latch Register 11.1.1.3. Table Read Operations 11.1.1.4. Table Write Operations 11.1.1.5. Table Pointer Boundaries 11.1.1.6. Reading the Program Flash Memory 11.1.2. NVM Unlock Sequence 11.1.3. Erasing Program Flash Memory 11.1.3.1. Program Flash Memory Erase Sequence 11.1.4. Writing to Program Flash Memory 11.1.4.1. Program Flash Memory Write Sequence 11.1.4.2. Write Verify 11.1.4.3. Unexpected Termination of Write Operation 11.1.4.4. Protection Against Spurious Writes 11.2. User ID, Device ID and Configuration Word Access 11.2.1. Reading Access 11.2.2. Writing Access 11.3. Data EEPROM Memory 11.3.1. NVMADR Register 11.3.2. NVMCON1 and NVMCON2 Registers 11.3.3. Reading the Data EEPROM Memory 11.3.4. Writing to the Data EEPROM Memory 11.3.5. Write Verify 11.3.6. Operation During Code-Protect 11.3.7. Protection Against Spurious Write 11.3.8. Erasing the Data EEPROM Memory 11.4. Register Summary: NVM Control 11.5. Register Definitions: Nonvolatile Memory 11.5.1. NVMCON1 11.5.2. NVMCON2 11.5.3. NVMADR 11.5.4. NVMDAT 11.5.5. TBLPTR 11.5.6. TABLAT 12. 8x8 Hardware Multiplier 12.1. Introduction 12.2. Operation 12.3. Register Summary - 8x8 Hardware Multiplier 12.4. Register Definitions: 8x8 Hardware Multiplier 12.4.1. PROD 13. (CRC) Cyclic Redundancy Check Module with Memory Scanner 13.1. CRC Module Overview 13.2. CRC Functional Overview 13.3. CRC Polynomial Implementation 13.4. CRC Data Sources 13.4.1. CRC from User Data 13.4.2. CRC from Flash 13.5. CRC Check Value 13.6. CRC Interrupt 13.7. Configuring the CRC 13.8. Program Memory Scan Configuration 13.9. Scanner Interrupt 13.10. Scanning Modes 13.10.1. Burst Mode 13.10.2. Concurrent Mode 13.10.3. Triggered mode 13.10.4. Peek Mode 13.10.5. Interrupt Interaction 13.10.6. WWDT interaction 13.10.7. In-Circuit Debug (ICD) Interaction 13.10.8. Peripheral Module Disable 13.11. Register Summary - CRC 13.12. Register Definitions: CRC and Scanner Control 13.12.1. CRCCON0 13.12.2. CRCCON1 13.12.3. CRCDAT 13.12.4. CRCACC 13.12.5. CRCSHIFT 13.12.6. CRCXOR 13.12.7. SCANCON0 13.12.8. SCANLADR 13.12.9. SCANHADR 13.12.10. SCANTRIG 14. Interrupts 14.1. Mid-Range Compatibility 14.2. Interrupt Priority 14.3. Interrupt Response 14.4. INTCON Registers 14.5. PIR Registers 14.6. PIE Registers 14.7. IPR Registers 14.8. INTn Pin Interrupts 14.9. TMR0 Interrupt 14.10. Interrupt-on-Change 14.11. Context Saving During Interrupts 14.12. Register Summary - Interrupt Control 14.13. Register Definitions: Interrupt Control 14.13.1. INTCON 14.13.2. PIR0 14.13.3. PIR1 14.13.4. PIR2 14.13.5. PIR3 14.13.6. PIR4 14.13.7. PIR5 14.13.8. PIR6 14.13.9. PIR7 14.13.10. PIR8 14.13.11. PIR9 14.13.12. PIE0 14.13.13. PIE1 14.13.14. PIE2 14.13.15. PIE3 14.13.16. PIE4 14.13.17. PIE5 14.13.18. PIE6 14.13.19. PIE7 14.13.20. PIE8 14.13.21. PIE9 14.13.22. IPR0 14.13.23. IPR1 14.13.24. IPR2 14.13.25. IPR3 14.13.26. IPR4 14.13.27. IPR5 14.13.28. IPR6 14.13.29. IPR7 14.13.30. IPR8 14.13.31. IPR9 15. I/O Ports 15.1. I/O Priorities 15.2. PORTx Registers 15.2.1. Data Register 15.2.2. Direction Control 15.2.3. Analog Control 15.2.4. Open-Drain Control 15.2.5. Slew Rate Control 15.2.6. Input Threshold Control 15.2.7. Weak Pull-up Control 15.2.8. Edge Selectable Interrupt-on-Change 15.3. Register Summary - Input/Output 15.4. Register Definitions: Port Control 15.4.1. PORTA 15.4.2. PORTB 15.4.3. PORTC 15.4.4. PORTD 15.4.5. PORTE 15.4.6. PORTF 15.4.7. PORTG 15.4.8. PORTH 15.4.9. TRISA 15.4.10. TRISB 15.4.11. TRISC 15.4.12. TRISD 15.4.13. TRISE 15.4.14. TRISF 15.4.15. TRISG 15.4.16. TRISH 15.4.17. LATA 15.4.18. LATB 15.4.19. LATC 15.4.20. LATD 15.4.21. LATE 15.4.22. LATF 15.4.23. LATG 15.4.24. LATH 15.4.25. ANSELA 15.4.26. ANSELB 15.4.27. ANSELD 15.4.28. ANSELE 15.4.29. ANSELF 15.4.30. ANSELG 15.4.31. WPUA 15.4.32. WPUB 15.4.33. WPUC 15.4.34. WPUD 15.4.35. WPUE 15.4.36. WPUF 15.4.37. WPUG 15.4.38. WPUH 15.4.39. ODCONA 15.4.40. ODCONB 15.4.41. ODCONC 15.4.42. ODCOND 15.4.43. ODCONE 15.4.44. ODCONF 15.4.45. ODCONG 15.4.46. ODCONH 15.4.47. SLRCONA 15.4.48. SLRCONB 15.4.49. SLRCONC 15.4.50. SLRCOND 15.4.51. SLRCONE 15.4.52. SLRCONF 15.4.53. SLRCONG 15.4.54. SLRCONH 15.4.55. INLVLA 15.4.56. INLVLB 15.4.57. INLVLC 15.4.58. INLVLD 15.4.59. INLVLE 15.4.60. INLVLF 15.4.61. INLVLG 15.4.62. INLVLH 16. Interrupt-on-Change 16.1. Features 16.2. Overview 16.3. Block Diagram 16.4. Enabling the Module 16.5. Individual Pin Configuration 16.6. Interrupt Flags 16.7. Clearing Interrupt Flags 16.8. Operation in Sleep 16.9. Register Summary - Interrupt-on-Change 16.10. Register Definitions: Interrupt-on-Change Control 16.10.1. IOCAF 16.10.2. IOCBF 16.10.3. IOCCF 16.10.4. IOCEF 16.10.5. IOCGF 16.10.6. IOCAN 16.10.7. IOCBN 16.10.8. IOCCN 16.10.9. IOCEN 16.10.10. IOCGN 16.10.11. IOCAP 16.10.12. IOCBP 16.10.13. IOCCP 16.10.14. IOCEP 16.10.15. IOCGP 17. (PPS) Peripheral Pin Select Module 17.1. PPS Inputs 17.2. PPS Outputs 17.3. Bidirectional Pins 17.4. PPS Lock 17.5. PPS One-Way Lock 17.6. Operation During Sleep 17.7. Effects of a Reset 17.8. Register Definitions: PPS Input and Output Selection 17.8.1. Register Summary - PPS 17.8.2. Peripheral xxx Input Selection 17.8.3. Pin Rxy Output Source Selection Register 17.8.4. PPS Lock Register 18. Resets 18.1. Power-on Reset (POR) 18.2. Brown-out Reset (BOR) 18.2.1. BOR is Always On 18.2.2. BOR is OFF in Sleep 18.2.3. BOR Controlled by Software 18.2.4. BOR and Bulk Erase 18.3. Low-Power Brown-out Reset (LPBOR) 18.3.1. Enabling LPBOR 18.3.1.1. LPBOR Module Output 18.4. MCLR 18.4.1. MCLR Enabled 18.4.2. MCLR Disabled 18.5. Windowed Watchdog Timer (WWDT) Reset 18.6. RESET Instruction 18.7. Stack Overflow/Underflow Reset 18.8. Programming Mode Exit 18.9. Power-up Timer (PWRT) 18.10. Start-up Sequence 18.11. Determining the Cause of a Reset 18.12. Power Control (PCON0) Register 18.13. Register Summary - BOR Control and Power Control 18.14. Register Definitions: Power Control 18.14.1. BORCON 18.14.2. PCON0 19. Timer0 Module 19.1. Timer0 Operation 19.1.1. 8-bit Mode 19.1.2. 16-Bit Mode 19.2. Clock Selection 19.2.1. Clock Source Selection 19.2.2. Synchronous Mode 19.2.3. Asynchronous Mode 19.2.4. Programmable Prescaler 19.3. Timer0 Output and Interrupt 19.3.1. Programmable Postscaler 19.3.2. Timer0 Output 19.3.3. Timer0 Interrupt 19.3.4. Timer0 Example 19.4. Operation During Sleep 19.5. Register Summary - Timer0 19.6. Register Definitions: Timer0 Control 19.6.1. T0CON0 19.6.2. T0CON1 19.6.3. TMR0 20. Timer1 Module with Gate Control 20.1. Timer1 Operation 20.2. Clock Source Selection 20.2.1. Internal Clock Source 20.2.2. External Clock Source 20.3. Timer1 Prescaler 20.4. Secondary Oscillator 20.5. Timer1 Operation in Asynchronous Counter Mode 20.5.1. Reading and Writing Timer1 in Asynchronous Counter Mode 20.6. Timer1 16-Bit Read/Write Mode 20.7. Timer1 Gate 20.7.1. Timer1 Gate Enable 20.7.2. Timer1 Gate Source Selection 20.7.3. Timer1 Gate Toggle Mode 20.7.4. Timer1 Gate Single-Pulse Mode 20.7.5. Timer1 Gate Value Status 20.7.6. Timer1 Gate Event Interrupt 20.8. Timer1 Interrupt 20.9. Timer1 Operation During Sleep 20.10. CCP Capture/Compare Time Base 20.11. CCP Special Event Trigger 20.12. Peripheral Module Disable 20.13. Register Summary - Timer1 20.14. Register Definitions: Timer1 20.14.1. TxCON 20.14.2. TxGCON 20.14.3. TMRxCLK 20.14.4. TMRxGATE 20.14.5. TMRx 21. Timer2 Module 21.1. Timer2 Operation 21.1.1. Free Running Period Mode 21.1.2. One-Shot Mode 21.1.3. Monostable Mode 21.2. Timer2 Output 21.3. External Reset Sources 21.4. Timer2 Interrupt 21.5. Operating Modes 21.6. Operation Examples 21.6.1. Software Gate Mode 21.6.2. Hardware Gate Mode 21.6.3. Edge-Triggered Hardware Limit Mode 21.6.4. Level-Triggered Hardware Limit Mode 21.6.5. Software Start One-Shot Mode 21.6.6. Edge-Triggered One-Shot Mode 21.6.7. Edge-Triggered Hardware Limit One-Shot Mode 21.6.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 21.6.9. Edge-Triggered Monostable Modes 21.6.10. Level-Triggered Hardware Limit One-Shot Modes 21.7. Timer2 Operation During Sleep 21.8. Register Summary - Timer2 21.9. Register Definitions: Timer2 Control 21.9.1. TxTMR 21.9.2. TxPR 21.9.3. TxCON 21.9.4. TxHLT 21.9.5. TxCLKCON 21.9.6. TxRST 22. Capture/Compare/PWM Module 22.1. CCP Module Configuration 22.1.1. CCP Modules and Timer Resources 22.1.2. Open-Drain Output Option 22.2. Capture Mode 22.2.1. Capture Sources 22.2.2. Timer1 Mode Resource 22.2.3. Software Interrupt Mode 22.2.4. CCP Prescaler 22.2.5. Capture During Sleep 22.3. Compare Mode 22.3.1. CCPx Pin Configuration 22.3.2. Timer1 Mode Resource 22.3.3. Auto-Conversion Trigger 22.3.4. Compare During Sleep 22.4. PWM Overview 22.4.1. Standard PWM Operation 22.4.2. Setup for PWM Operation 22.4.3. Timer2 Timer Resource 22.4.4. PWM Period 22.4.5. PWM Duty Cycle 22.4.6. PWM Resolution 22.4.7. Operation in Sleep Mode 22.4.8. Changes in System Clock Frequency 22.4.9. Effects of Reset 22.5. Register Summary - CCP Control 22.6. Register Definitions: CCP Control 22.6.1. CCPxCON 22.6.2. CCPxCAP 22.6.3. CCPRx 22.6.4. CCPTMRS0 22.6.5. CCPTMRS1 23. (PWM) Pulse-Width Modulation 23.1. Fundamental Operation 23.2. PWM Output Polarity 23.3. PWM Period 23.4. PWM Duty Cycle 23.5. PWM Resolution 23.6. Operation in Sleep Mode 23.7. Changes in System Clock Frequency 23.8. Effects of Reset 23.9. Setup for PWM Operation using PWMx Output Pins 23.9.1. PWMx Pin Configuration 23.10. Setup for PWM Operation to Other Device Peripherals 23.11. Register Summary - Registers Associated with PWM 23.12. Register Definitions: PWM Control 23.12.1. PWMxCON 23.12.2. CCPTMRS0 23.12.3. CCPTMRS1 23.12.4. PWMxDC 24. (ZCD) Zero-Cross Detection Module 24.1. External Resistor Selection 24.2. ZCD Logic Output 24.3. ZCD Logic Polarity 24.4. ZCD Interrupts 24.5. Correction for ZCPINV Offset 24.5.1. Correction by AC Coupling 24.5.2. Correction By Offset Current 24.6. Handling VPEAK Variations 24.7. Operation During Sleep 24.8. Effects of a Reset 24.9. Disabling the ZCD Module 24.10. Register Summary: ZCD Control 24.11. Register Definitions: ZCD Control 24.11.1. ZCDCON 25. (CWG) Complementary Waveform Generator Module 25.1. Fundamental Operation 25.2. Operating Modes 25.2.1. Half-Bridge Mode 25.2.2. Push-Pull Mode 25.2.3. Full-Bridge Modes 25.2.3.1. Direction Change in Full-Bridge Mode 25.2.3.2. Dead-Band Delay in Full-Bridge Mode 25.2.4. Steering Modes 25.2.4.1. Synchronous Steering Mode 25.2.4.2. Asynchronous Steering Mode 25.3. Start-up Considerations 25.4. Clock Source 25.5. Selectable Input Sources 25.6. Output Control 25.6.1. CWG Outputs 25.6.2. Polarity Control 25.7. Dead-Band Control 25.7.1. Dead-Band Functionality in Half-Bridge mode 25.7.2. Dead-Band Functionality in Full-Bridge mode 25.8. Rising Edge and Reverse Dead Band 25.9. Falling Edge and Forward Dead Band 25.10. Dead-Band Jitter 25.11. Auto-Shutdown 25.11.1. Shutdown 25.11.1.1. Software Generated Shutdown 25.11.1.2. External Input Source 25.11.1.3. Pin Override Levels 25.11.1.4. Auto-Shutdown Interrupts 25.11.2. Auto-Shutdown Restart 25.11.2.1. Software-Controlled Restart 25.11.2.2. Auto-Restart 25.12. Operation During Sleep 25.13. Configuring the CWG 25.14. Register Summary - CWG Control 25.15. Register Definitions: CWG Control 25.15.1. CWGxCON0 25.15.2. CWGxCON1 25.15.3. CWGxCLKCON 25.15.4. CWGxISM 25.15.5. CWGxSTR 25.15.6. CWGxAS0 25.15.7. CWGxAS1 25.15.8. CWGxDBR 25.15.9. CWGxDBF 26. (SMT) Signal Measurement Timer 26.1. SMT Operation 26.1.1. Clock Source Selection 26.1.2. Signal and Window Source Selection 26.1.3. Time Base 26.1.4. Capture Pulse Width and Period Registers 26.1.5. Status Information 26.1.6. Modes of Operation 26.1.6.1. Timer Mode 26.1.6.2. Gated Timer Mode 26.1.6.3. Period and Duty Cycle Measurement Mode 26.1.6.4. High and Low Measurement Mode 26.1.6.5. Windowed Measurement Mode 26.1.6.6. Gated Window Measurement Mode 26.1.6.7. Time of Flight Measurement Mode 26.1.6.8. Capture Mode 26.1.6.9. Counter Mode 26.1.6.10. Gated Counter Mode 26.1.6.11. Windowed Counter Mode 26.1.7. Interrupts 26.1.8. Operation During Sleep 26.2. Register Summary - SMT Control 26.3. Register Definitions: SMT Control 26.3.1. SMTxCON0 26.3.2. SMTxCON1 26.3.3. SMTxSTAT 26.3.4. SMTxCLK 26.3.5. SMTxWIN 26.3.6. SMTxSIG 26.3.7. SMTxTMR 26.3.8. SMTxCPR 26.3.9. SMTxCPW 26.3.10. SMTxPR 27. (DSM) Data Signal Modulator Module 27.1. DSM Operation 27.2. Modulator Signal Sources 27.3. Carrier Signal Sources 27.4. Carrier Synchronization 27.5. Carrier Source Polarity Select 27.6. Programmable Modulator Data 27.7. Modulated Output Polarity 27.8. Operation in Sleep Mode 27.9. Effects of a Reset 27.10. Peripheral Module Disable 27.11. Register Summary - DSM 27.12. Register Definitions: Modulation Control 27.12.1. MDCON0 27.12.2. MDCON1 27.12.3. MDCARH 27.12.4. MDCARL 27.12.5. MDSRC 28. (MSSP) Master Synchronous Serial Port Module 28.1. SPI Mode Overview 28.1.1. SPI Mode Registers 28.2. SPI Mode Operation 28.2.1. SPI Master Mode 28.2.2. SPI Slave Mode 28.2.3. Daisy-Chain Configuration 28.2.4. Slave Select Synchronization 28.2.5. SPI Operation in Sleep Mode 28.3. I2C Mode Overview 28.3.1. Register Definitions: I2C Mode 28.4. I2C Mode Operation 28.4.1. Clock Stretching 28.4.2. Arbitration 28.4.3. Byte Format 28.4.4. Definition of I2C Terminology 28.4.5. SDA and SCL Pins 28.4.6. SDA Hold Time 28.4.7. Start Condition 28.4.8. Stop Condition 28.4.9. Restart Condition 28.4.10. Start/Stop Condition Interrupt Masking 28.4.11. Acknowledge Sequence 28.5. I2C Slave Mode Operation 28.5.1. Slave Mode Addresses 28.5.1.1. I2C Slave 7-bit Addressing Mode 28.5.1.2. I2C Slave 10-bit Addressing Mode 28.5.2. Slave Reception 28.5.2.1. 7-bit Addressing Reception 28.5.2.2. 7-bit Reception with AHEN and DHEN 28.5.3. Slave Transmission 28.5.3.1. Slave Mode Bus Collision 28.5.3.2. 7-bit Transmission 28.5.3.3. 7-bit Transmission with Address Hold Enabled 28.5.4. Slave Mode 10-bit Address Reception 28.5.5. 10-bit Addressing with Address or Data Hold 28.5.6. Clock Stretching 28.5.6.1. Normal Clock Stretching 28.5.6.2. 10-bit Addressing Mode 28.5.6.3. Byte NACKing 28.5.7. Clock Synchronization and the CKP bit 28.5.8. General Call Address Support 28.5.9. SSP Mask Register 28.6. I2C Master Mode 28.6.1. I2C Master Mode Operation 28.6.2. Clock Arbitration 28.6.3. WCOL Status Flag 28.6.4. I2C Master Mode Start Condition Timing 28.6.5. I2C Master Mode Repeated Start Condition Timing 28.6.6. I2C Master Mode Transmission 28.6.6.1. BF Status Flag 28.6.6.2. WCOL Status Flag 28.6.6.3. ACKSTAT Status Flag 28.6.6.4. Typical transmit sequence: 28.6.7. I2C Master Mode Reception 28.6.7.1. BF Status Flag 28.6.7.2. SSPOV Status Flag 28.6.7.3. WCOL Status Flag 28.6.7.4. Typical Receive Sequence: 28.6.8. Acknowledge Sequence Timing 28.6.8.1. Acknowledge Write Collision 28.6.9. Stop Condition Timing 28.6.9.1. Write Collision on Stop 28.6.10. Sleep Operation 28.6.11. Effects of a Reset 28.6.12. Multi-Master Mode 28.6.13. Multi -Master Communication, Bus Collision and Bus Arbitration 28.6.13.1. Bus Collision During a Start Condition 28.6.13.2. Bus Collision During a Repeated Start Condition 28.6.13.3. Bus Collision During a Stop Condition 28.7. Baud Rate Generator 28.8. Register Summary: MSSP Control 28.9. Register Definitions: MSSP Control 28.9.1. SSPxSTAT 28.9.2. SSPxCON1 28.9.3. SSPxCON2 28.9.4. SSPxCON3 28.9.5. SSPxBUF 28.9.6. SSPxADD 28.9.7. SSPxMSK 29. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter 29.1. EUSART Asynchronous Mode 29.1.1. EUSART Asynchronous Transmitter 29.1.1.1. Enabling the Transmitter 29.1.1.2. Transmitting Data 29.1.1.3. Transmit Data Polarity 29.1.1.4. Transmit Interrupt Flag 29.1.1.5. TSR Status 29.1.1.6. Transmitting 9-Bit Characters 29.1.1.7. Asynchronous Transmission Setup 29.1.2. EUSART Asynchronous Receiver 29.1.2.1. Enabling the Receiver 29.1.2.2. Receiving Data 29.1.2.3. Receive Interrupts 29.1.2.4. Receive Framing Error 29.1.2.5. Receive Overrun Error 29.1.2.6. Receiving 9-Bit Characters 29.1.2.7. Address Detection 29.1.2.8. Asynchronous Reception Setup 29.1.2.9. 9-Bit Address Detection Mode Setup 29.1.3. Clock Accuracy with Asynchronous Operation 29.2. EUSART Baud Rate Generator (BRG) 29.2.1. Auto-Baud Detect 29.2.2. Auto-Baud Overflow 29.2.3. Auto-Wake-up on Break 29.2.3.1. Special Considerations 29.2.4. Break Character Sequence 29.2.4.1. Break and Sync Transmit Sequence 29.2.5. Receiving a Break Character 29.3. EUSART Synchronous Mode 29.3.1. Synchronous Master Mode 29.3.1.1. Master Clock 29.3.1.2. Clock Polarity 29.3.1.3. Synchronous Master Transmission 29.3.1.4. Synchronous Master Transmission Setup 29.3.1.5. Synchronous Master Reception 29.3.1.6. Receive Overrun Error 29.3.1.7. Receiving 9-Bit Characters 29.3.1.8. Synchronous Master Reception Setup 29.3.2. Synchronous Slave Mode 29.3.2.1. Slave Clock 29.3.2.2. EUSART Synchronous Slave Transmit 29.3.2.3. Synchronous Slave Transmission Setup 29.3.2.4. EUSART Synchronous Slave Reception 29.3.2.5. Synchronous Slave Reception Setup: 29.4. EUSART Operation During Sleep 29.4.1. Synchronous Receive During Sleep 29.4.2. Synchronous Transmit During Sleep 29.5. Register Summary - EUSART 29.6. Register Definitions: EUSART Control 29.6.1. RCxSTA 29.6.2. TXxSTA 29.6.3. BAUDxCON 29.6.4. SPxBRG 29.6.5. RCxREG 29.6.6. TXxREG 30. (FVR) Fixed Voltage Reference 30.1. Independent Gain Amplifiers 30.2. FVR Stabilization Period 30.3. Register Summary - FVR 30.4. Register Definitions: FVR Control 30.4.1. FVRCON 31. Temperature Indicator Module 31.1. Circuit Operation 31.2. Minimum Operating VDD 31.3. Temperature Output 31.4. ADC Acquisition Time 32. (DAC) 5-Bit Digital-to-Analog Converter Module 32.1. Output Voltage Selection 32.2. Ratiometric Output Level 32.3. DAC Voltage Reference Output 32.4. Operation During Sleep 32.5. Effects of a Reset 32.6. Register Summary - DAC Control 32.7. Register Definitions: DAC Control 32.7.1. DAC1CON0 32.7.2. DAC1CON1 33. (ADC2) Analog-to-Digital Converter with Computation Module 33.1. ADC Configuration 33.1.1. Port Configuration 33.1.2. Channel Selection 33.1.3. ADC Voltage Reference 33.1.4. Conversion Clock 33.1.5. Interrupts 33.1.6. Result Formatting 33.2. ADC Operation 33.2.1. Starting a Conversion 33.2.2. Completion of a Conversion 33.2.3. Terminating a Conversion 33.2.4. ADC Operation During Sleep 33.2.5. External Trigger During Sleep 33.2.6. Auto-Conversion Trigger 33.2.7. ADC Conversion Procedure (Basic Mode) 33.3. ADC Acquisition Requirements 33.4. Capacitive Voltage Divider (CVD) Features 33.4.1. CVD Operation 33.4.2. PreCharge Control 33.4.3. Acquisition Control for CVD (ADPRE > 0) 33.4.4. Guard Ring Outputs 33.4.5. Additional Sample and Hold Capacitance 33.5. Computation Operation 33.5.1. Digital Filter/Average 33.5.2. Basic Mode 33.5.3. Accumulate Mode 33.5.4. Average Mode 33.5.5. Burst Average Mode 33.5.6. Low-pass Filter Mode 33.5.7. Threshold Comparison 33.5.8. Continuous Sampling Mode 33.5.9. Double Sample Conversion 33.6. Register Summary - ADC Control 33.7. Register Definitions: ADC Control 33.7.1. ADCON0 33.7.2. ADCON1 33.7.3. ADCON2 33.7.4. ADCON3 33.7.5. ADSTAT 33.7.6. ADCLK 33.7.7. ADREF 33.7.8. ADPCH 33.7.9. ADPRE 33.7.10. ADACQ 33.7.11. ADCAP 33.7.12. ADRPT 33.7.13. ADCNT 33.7.14. ADFLTR 33.7.15. ADRES 33.7.16. ADPREV 33.7.17. ADACC 33.7.18. ADSTPT 33.7.19. ADERR 33.7.20. ADLTH 33.7.21. ADUTH 33.7.22. ADACT 34. (CMP) Comparator Module 34.1. Comparator Overview 34.2. Comparator Control 34.2.1. Comparator Enable 34.2.2. Comparator Output 34.2.3. Comparator Output Polarity 34.3. Comparator Hysteresis 34.4. Operation With Timer1 Gate 34.4.1. Comparator Output Synchronization 34.5. Comparator Interrupt 34.6. Comparator Positive Input Selection 34.7. Comparator Negative Input Selection 34.8. Comparator Response Time 34.9. Analog Input Connection Considerations 34.10. CWG1 Auto-Shutdown Source 34.11. ADC Auto-Trigger Source 34.12. Even Numbered Timers Reset 34.13. Operation in Sleep Mode 34.14. Register Summary - Comparator 34.15. Register Definitions: Comparator Control 34.15.1. CMxCON0 34.15.2. CMxCON1 34.15.3. CMxNCH 34.15.4. CMxPCH 34.15.5. CMOUT 35. (HLVD) High/Low-Voltage Detect 35.1. Operation 35.2. Setup 35.3. Current Consumption 35.4. HLVD Start-up Time 35.5. Applications 35.6. Operation During Sleep 35.7. Operation During Idle and Doze Modes 35.8. Effects of a Reset 35.9. Register Summary - HLVD 35.10. Register Definitions: HLVD Control 35.10.1. HLVDCON0 35.10.2. HLVDCON1 36. Register Summary 37. In-Circuit Serial Programming™ (ICSP™) 37.1. High-Voltage Programming Entry Mode 37.2. Low-Voltage Programming Entry Mode 37.3. Common Programming Interfaces 38. Instruction Set Summary 38.1. Standard Instruction Set 38.1.1. Standard Instruction Set 38.2. Extended Instruction Set 38.2.1. Extended Instruction Syntax 38.2.2. Extended Instruction Set 38.2.3. Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode 38.2.3.1. Extended Instruction Syntax with Standard PIC18 Commands 38.2.4. Considerations when Enabling the Extended Instruction Set 38.2.5. Special Considerations with Microchip MPLAB® IDE Tools 39. Development Support 39.1. MPLAB X Integrated Development Environment Software 39.2. MPLAB XC Compilers 39.3. MPASM Assembler 39.4. MPLINK Object Linker/MPLIB Object Librarian 39.5. MPLAB Assembler, Linker and Librarian for Various Device Families 39.6. MPLAB X SIM Software Simulator 39.7. MPLAB REAL ICE In-Circuit Emulator System 39.8. MPLAB ICD 3 In-Circuit Debugger System 39.9. PICkit 3 In-Circuit Debugger/Programmer 39.10. MPLAB PM3 Device Programmer 39.11. Demonstration/Development Boards, Evaluation Kits, and Starter Kits 39.12. Third-Party Development Tools 40. Electrical Specifications 40.1. Absolute Maximum Ratings(†) 40.2. Standard Operating Conditions 40.3. DC Characteristics 40.3.1. Supply Voltage 40.3.2. Supply Current (IDD)(1,2,4) 40.3.3. Power-Down Current (IPD)(1,2) 40.3.4. I/O Ports 40.3.5. Memory Programming Specifications 40.3.6. Thermal Characteristics 40.4. AC Characteristics 40.4.1. External Clock/Oscillator Timing Requirements 40.4.2. Internal Oscillator Parameters(1) 40.4.3. PLL Specifications 40.4.4. I/O and CLKOUT Timing Specifications 40.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 40.4.6. High/Low-Voltage Detect Characteristics 40.4.7. Analog-To-Digital Converter (ADC) Accuracy Specifications(1,2) 40.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 40.4.9. Comparator Specifications 40.4.10. 5-Bit DAC Specifications 40.4.11. Fixed Voltage Reference (FVR) Specifications 40.4.12. Zero Cross Detect (ZCD) Specifications 40.4.13. Timer0 and Timer1 External Clock Requirements 40.4.14. Capture/Compare/PWM Requirements (CCP) 40.4.15. EUSART Synchronous Transmission Requirements 40.4.16. EUSART Synchronous Receive Requirements 40.4.17. SPI Mode Requirements 40.4.18. I2C Bus Start/Stop Bits Requirements 40.4.19. I2C Bus Data Requirements 41. DC and AC Characteristics Graphs and Tables 41.1. Graphs 42. Packaging Information 42.1. Package Details 43. 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These PIC18(L)F65/66K40 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications. These 64-pin devices are equipped with a 10-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They also offer a set of Core Independent Peripherals such as Complementary Waveform Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross Detect (ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system cost.
Core Features
• C Compiler Optimized RISC Architecture • Operating Speed: – DC – 64 MHz clock input over the full VDD range – 62.5 ns minimum instruction cycle • Programmable 2-Level Interrupt Priority • 31-Level Deep Hardware Stack • Four 8-Bit Timers (TMR2/4/6/7) with Hardware Limit Timer (HLT) • Five 16-Bit Timers (TMR0/1/3/5/7) • Low-Current Power-on Reset (POR) • Power-up Timer (PWRT) • Brown-out Reset (BOR) • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): – Watchdog Reset on too long or too short interval between watchdog clear events – Variable prescaler selection – Variable window size selection – All sources configurable in hardware or software
Memory
• Up to 64k bytes Program Flash Memory • Up to 3562 Bytes Data SRAM Memory • 1024 Bytes Data EEPROM © 2017 Microchip Technology Inc.
Datasheet
DS40001842D-page 1 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Operation Modes eXtreme Low-Power (XLP) Features Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features PIC18(L)F65/66K40 Family Types Pin Diagrams Pin Allocation Tables Table of Contents 1. Device Overview 1.1. New Core Features 1.1.1. XLP Technology 1.1.2. Multiple Oscillator Options and Features 1.2. Other Special Features 1.3. Details on Individual Family Members 1.4. Register and Bit naming conventions 1.4.1. Register Names 1.4.2. Bit Names 1.4.2.1. Short Bit Names 1.4.2.2. Long Bit Names 1.4.2.3. Bit Fields 1.4.3. Register and Bit Naming Exceptions 1.4.3.1. Status, Interrupt, and Mirror Bits 1.4.3.2. Legacy Peripherals 2. Guidelines for Getting Started with PIC18(L)F65/66K40 Microcontrollers 2.1. Basic Connection Requirements 2.2. Power Supply Pins 2.2.1. Decoupling Capacitors 2.2.2. Tank Capacitors 2.3. Master Clear (MCLR) Pin 2.4. ICSP™ Pins 2.5. External Oscillator Pins 2.6. Unused I/Os 3. Device Configuration 3.1. Configuration Words 3.2. Code Protection 3.2.1. Program Memory Protection 3.2.2. Data memory protection 3.3. Write Protection 3.4. User ID 3.5. Device ID and Revision ID 3.6. Register Summary - Configuration Words 3.7. Register Definitions: Configuration Words 3.7.1. CONFIG1 3.7.2. CONFIG2 3.7.3. CONFIG3 3.7.4. CONFIG4 3.7.5. CONFIG5 3.7.6. CONFIG6 3.8. Register Summary - Device and Revision 3.9. Register Definitions: Device and Revision 3.9.1. DEVICE ID 3.9.2. REVISION ID 4. Oscillator Module (with Fail-Safe Clock Monitor) 4.1. Overview 4.2. Clock Source Types 4.2.1. External Clock Sources 4.2.1.1. EC Mode 4.2.1.2. LP, XT, HS Modes 4.2.1.3. Oscillator Start-up Timer (OST) 4.2.1.4. 4x PLL 4.2.1.5. Secondary Oscillator 4.2.2. Internal Clock Sources 4.2.2.1. HFINTOSC 4.2.2.2. MFINTOSC 4.2.2.3. LFINTOSC 4.2.2.4. ADCRC (also referred to as FRC) 4.2.3. Oscillator Status and Adjustments 4.2.3.1. Internal Oscillator Frequency Adjustment 4.2.3.2. Oscillator Status and Manual Enable 4.2.3.3. HFOR and MFOR Bits 4.3. Clock Switching 4.3.1. New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits 4.3.2. PLL Input Switch 4.3.3. Clock Switch and Sleep 4.4. Fail-Safe Clock Monitor 4.4.1. Fail-Safe Detection 4.4.2. Fail-Safe Operation 4.4.3. Fail-Safe Condition Clearing 4.4.4. Reset or Wake-up from Sleep 4.5. Register Summary - OSC 4.6. Register Definitions: Oscillator Control 4.6.1. OSCCON1 4.6.2. OSCCON2 4.6.3. OSCCON3 4.6.4. OSCSTAT 4.6.5. OSCFRQ 4.6.6. OSCTUNE 4.6.7. OSCEN 5. Reference Clock Output Module 5.1. Clock Source 5.1.1. Clock Synchronization 5.2. Programmable Clock Divider 5.3. Selectable Duty Cycle 5.4. Operation in Sleep Mode 5.5. Register Summary: Reference CLK 5.6. Register Definitions: Reference Clock 5.6.1. CLKRCON 5.6.2. CLKRCLK 6. Power-Saving Operation Modes 6.1. Doze Mode 6.1.1. Doze Operation 6.1.2. Interrupts During Doze 6.2. Sleep Mode 6.2.1. Wake-up from Sleep 6.2.2. Wake-up Using Interrupts 6.2.3. Low-Power Sleep Mode 6.2.3.1. Sleep Current vs. Wake-up Time 6.2.3.2. Peripheral Usage in Sleep 6.2.4. Idle Mode 6.2.4.1. Idle and Interrupts 6.2.4.2. Idle and WWDT 6.3. Peripheral Operation in Power-Saving Modes 6.4. Register Summary - Power Savings Control 6.5. Register Definitions: Power Savings Control 6.5.1. VREGCON 6.5.2. CPUDOZE 7. (PMD) Peripheral Module Disable 7.1. Disabling a Module 7.2. Enabling a Module 7.3. Register Summary - PMD 7.4. Register Definitions: Peripheral Module Disable 7.4.1. PMD0 7.4.2. PMD1 7.4.3. PMD2 7.4.4. PMD3 7.4.5. PMD4 7.4.6. PMD5 8. Resets 8.1. Power-on Reset (POR) 8.2. Brown-out Reset (BOR) 8.2.1. BOR is Always On 8.2.2. BOR is OFF in Sleep 8.2.3. BOR Controlled by Software 8.2.4. BOR and Bulk Erase 8.3. Low-Power Brown-out Reset (LPBOR) 8.3.1. Enabling LPBOR 8.3.1.1. LPBOR Module Output 8.4. MCLR 8.4.1. MCLR Enabled 8.4.2. MCLR Disabled 8.5. Windowed Watchdog Timer (WWDT) Reset 8.6. RESET Instruction 8.7. Stack Overflow/Underflow Reset 8.8. Programming Mode Exit 8.9. Power-up Timer (PWRT) 8.10. Start-up Sequence 8.11. Determining the Cause of a Reset 8.12. Power Control (PCON0) Register 8.13. Register Summary - BOR Control and Power Control 8.14. Register Definitions: Power Control 8.14.1. BORCON 8.14.2. PCON0 9. (WWDT) Windowed Watchdog Timer 9.1. Independent Clock Source 9.2. WWDT Operating Modes 9.2.1. WWDT Is Always On 9.2.2. WWDT Is Off in Sleep 9.2.3. WWDT Controlled by Software 9.3. Time-out Period 9.4. Watchdog Window 9.5. Clearing the WWDT 9.5.1. CLRWDT Considerations (Windowed Mode) 9.6. Operation During Sleep 9.7. Register Summary - WDT Control 9.8. Register Definitions: Windowed Watchdog Timer Control 9.8.1. WDTCON0 9.8.2. WDTCON1 9.8.3. WDTPS 9.8.4. WDTTMR 10. Memory Organization 10.1. Program Memory Organization 10.1.1. Program Counter 10.1.2. Return Address Stack 10.1.2.1. Top-of-Stack Access 10.1.2.2. Return Stack Pointer 10.1.2.3. Stack Overflow and Underflow Resets 10.1.2.4. PUSH and POP Instructions 10.1.2.5. Fast Register Stack 10.1.3. Look-up Tables in Program Memory 10.1.3.1. Computed GOTO 10.1.3.2. Table Reads and Table Writes 10.2. PIC18 Instruction Cycle 10.2.1. Clocking Scheme 10.2.2. Instruction Flow/Pipelining 10.2.3. Instructions in Program Memory 10.2.4. Two-Word Instructions 10.3. Data Memory Organization 10.3.1. Bank Select Register 10.3.2. Access Bank 10.3.3. General Purpose Register File 10.3.4. Special Function Registers 10.3.5. Status Register 10.4. Data Addressing Modes 10.4.1. Inherent and Literal Addressing 10.4.2. Direct Addressing 10.4.3. Indirect Addressing 10.4.3.1. FSR Registers and the INDF Operand 10.4.3.2. FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 10.4.3.3. Operations by FSRs on FSRs 10.5. Data Memory and the Extended Instruction Set 10.5.1. Indexed Addressing with Literal Offset 10.5.2. Instructions Affected by Indexed Literal Offset Mode 10.5.3. Mapping the Access Bank in Indexed Literal Offset Mode 10.6. PIC18 Instruction Execution and the Extended Instruction Set 10.7. Register Summary: Memory and Status 10.8. Register Definitions: Memory and Status 10.8.1. PCL 10.8.2. PCLAT 10.8.3. TOS 10.8.4. STKPTR 10.8.5. STATUS 10.8.6. WREG 10.8.7. INDF 10.8.8. POSTDEC 10.8.9. POSTINC 10.8.10. PREINC 10.8.11. PLUSW 10.8.12. FSR 10.8.13. BSR 11. (NVM) Nonvolatile Memory Control 11.1. Program Flash Memory 11.1.1. Table Pointer Operations 11.1.1.1. Table Pointer Register 11.1.1.2. Table Latch Register 11.1.1.3. Table Read Operations 11.1.1.4. Table Write Operations 11.1.1.5. Table Pointer Boundaries 11.1.1.6. Reading the Program Flash Memory 11.1.2. NVM Unlock Sequence 11.1.3. Erasing Program Flash Memory 11.1.3.1. Program Flash Memory Erase Sequence 11.1.4. Writing to Program Flash Memory 11.1.4.1. Program Flash Memory Write Sequence 11.1.4.2. Write Verify 11.1.4.3. Unexpected Termination of Write Operation 11.1.4.4. Protection Against Spurious Writes 11.2. User ID, Device ID and Configuration Word Access 11.2.1. Reading Access 11.2.2. Writing Access 11.3. Data EEPROM Memory 11.3.1. NVMADR Register 11.3.2. NVMCON1 and NVMCON2 Registers 11.3.3. Reading the Data EEPROM Memory 11.3.4. Writing to the Data EEPROM Memory 11.3.5. Write Verify 11.3.6. Operation During Code-Protect 11.3.7. Protection Against Spurious Write 11.3.8. Erasing the Data EEPROM Memory 11.4. Register Summary: NVM Control 11.5. Register Definitions: Nonvolatile Memory 11.5.1. NVMCON1 11.5.2. NVMCON2 11.5.3. NVMADR 11.5.4. NVMDAT 11.5.5. TBLPTR 11.5.6. TABLAT 12. 8x8 Hardware Multiplier 12.1. Introduction 12.2. Operation 12.3. Register Summary - 8x8 Hardware Multiplier 12.4. Register Definitions: 8x8 Hardware Multiplier 12.4.1. PROD 13. (CRC) Cyclic Redundancy Check Module with Memory Scanner 13.1. CRC Module Overview 13.2. CRC Functional Overview 13.3. CRC Polynomial Implementation 13.4. CRC Data Sources 13.4.1. CRC from User Data 13.4.2. CRC from Flash 13.5. CRC Check Value 13.6. CRC Interrupt 13.7. Configuring the CRC 13.8. Program Memory Scan Configuration 13.9. Scanner Interrupt 13.10. Scanning Modes 13.10.1. Burst Mode 13.10.2. Concurrent Mode 13.10.3. Triggered mode 13.10.4. Peek Mode 13.10.5. Interrupt Interaction 13.10.6. WWDT interaction 13.10.7. In-Circuit Debug (ICD) Interaction 13.10.8. Peripheral Module Disable 13.11. Register Summary - CRC 13.12. Register Definitions: CRC and Scanner Control 13.12.1. CRCCON0 13.12.2. CRCCON1 13.12.3. CRCDAT 13.12.4. CRCACC 13.12.5. CRCSHIFT 13.12.6. CRCXOR 13.12.7. SCANCON0 13.12.8. SCANLADR 13.12.9. SCANHADR 13.12.10. SCANTRIG 14. Interrupts 14.1. Mid-Range Compatibility 14.2. Interrupt Priority 14.3. Interrupt Response 14.4. INTCON Registers 14.5. PIR Registers 14.6. PIE Registers 14.7. IPR Registers 14.8. INTn Pin Interrupts 14.9. TMR0 Interrupt 14.10. Interrupt-on-Change 14.11. Context Saving During Interrupts 14.12. Register Summary - Interrupt Control 14.13. Register Definitions: Interrupt Control 14.13.1. INTCON 14.13.2. PIR0 14.13.3. PIR1 14.13.4. PIR2 14.13.5. PIR3 14.13.6. PIR4 14.13.7. PIR5 14.13.8. PIR6 14.13.9. PIR7 14.13.10. PIR8 14.13.11. PIR9 14.13.12. PIE0 14.13.13. PIE1 14.13.14. PIE2 14.13.15. PIE3 14.13.16. PIE4 14.13.17. PIE5 14.13.18. PIE6 14.13.19. PIE7 14.13.20. PIE8 14.13.21. PIE9 14.13.22. IPR0 14.13.23. IPR1 14.13.24. IPR2 14.13.25. IPR3 14.13.26. IPR4 14.13.27. IPR5 14.13.28. IPR6 14.13.29. IPR7 14.13.30. IPR8 14.13.31. IPR9 15. I/O Ports 15.1. I/O Priorities 15.2. PORTx Registers 15.2.1. Data Register 15.2.2. Direction Control 15.2.3. Analog Control 15.2.4. Open-Drain Control 15.2.5. Slew Rate Control 15.2.6. Input Threshold Control 15.2.7. Weak Pull-up Control 15.2.8. Edge Selectable Interrupt-on-Change 15.3. Register Summary - Input/Output 15.4. Register Definitions: Port Control 15.4.1. PORTA 15.4.2. PORTB 15.4.3. PORTC 15.4.4. PORTD 15.4.5. PORTE 15.4.6. PORTF 15.4.7. PORTG 15.4.8. PORTH 15.4.9. TRISA 15.4.10. TRISB 15.4.11. TRISC 15.4.12. TRISD 15.4.13. TRISE 15.4.14. TRISF 15.4.15. TRISG 15.4.16. TRISH 15.4.17. LATA 15.4.18. LATB 15.4.19. LATC 15.4.20. LATD 15.4.21. LATE 15.4.22. LATF 15.4.23. LATG 15.4.24. LATH 15.4.25. ANSELA 15.4.26. ANSELB 15.4.27. ANSELD 15.4.28. ANSELE 15.4.29. ANSELF 15.4.30. ANSELG 15.4.31. WPUA 15.4.32. WPUB 15.4.33. WPUC 15.4.34. WPUD 15.4.35. WPUE 15.4.36. WPUF 15.4.37. WPUG 15.4.38. WPUH 15.4.39. ODCONA 15.4.40. ODCONB 15.4.41. ODCONC 15.4.42. ODCOND 15.4.43. ODCONE 15.4.44. ODCONF 15.4.45. ODCONG 15.4.46. ODCONH 15.4.47. SLRCONA 15.4.48. SLRCONB 15.4.49. SLRCONC 15.4.50. SLRCOND 15.4.51. SLRCONE 15.4.52. SLRCONF 15.4.53. SLRCONG 15.4.54. SLRCONH 15.4.55. INLVLA 15.4.56. INLVLB 15.4.57. INLVLC 15.4.58. INLVLD 15.4.59. INLVLE 15.4.60. INLVLF 15.4.61. INLVLG 15.4.62. INLVLH 16. Interrupt-on-Change 16.1. Features 16.2. Overview 16.3. Block Diagram 16.4. Enabling the Module 16.5. Individual Pin Configuration 16.6. Interrupt Flags 16.7. Clearing Interrupt Flags 16.8. Operation in Sleep 16.9. Register Summary - Interrupt-on-Change 16.10. Register Definitions: Interrupt-on-Change Control 16.10.1. IOCAF 16.10.2. IOCBF 16.10.3. IOCCF 16.10.4. IOCEF 16.10.5. IOCGF 16.10.6. IOCAN 16.10.7. IOCBN 16.10.8. IOCCN 16.10.9. IOCEN 16.10.10. IOCGN 16.10.11. IOCAP 16.10.12. IOCBP 16.10.13. IOCCP 16.10.14. IOCEP 16.10.15. IOCGP 17. (PPS) Peripheral Pin Select Module 17.1. PPS Inputs 17.2. PPS Outputs 17.3. Bidirectional Pins 17.4. PPS Lock 17.5. PPS One-Way Lock 17.6. Operation During Sleep 17.7. Effects of a Reset 17.8. Register Definitions: PPS Input and Output Selection 17.8.1. Register Summary - PPS 17.8.2. Peripheral xxx Input Selection 17.8.3. Pin Rxy Output Source Selection Register 17.8.4. PPS Lock Register 18. Resets 18.1. Power-on Reset (POR) 18.2. Brown-out Reset (BOR) 18.2.1. BOR is Always On 18.2.2. BOR is OFF in Sleep 18.2.3. BOR Controlled by Software 18.2.4. BOR and Bulk Erase 18.3. Low-Power Brown-out Reset (LPBOR) 18.3.1. Enabling LPBOR 18.3.1.1. LPBOR Module Output 18.4. MCLR 18.4.1. MCLR Enabled 18.4.2. MCLR Disabled 18.5. Windowed Watchdog Timer (WWDT) Reset 18.6. RESET Instruction 18.7. Stack Overflow/Underflow Reset 18.8. Programming Mode Exit 18.9. Power-up Timer (PWRT) 18.10. Start-up Sequence 18.11. Determining the Cause of a Reset 18.12. Power Control (PCON0) Register 18.13. Register Summary - BOR Control and Power Control 18.14. Register Definitions: Power Control 18.14.1. BORCON 18.14.2. PCON0 19. Timer0 Module 19.1. Timer0 Operation 19.1.1. 8-bit Mode 19.1.2. 16-Bit Mode 19.2. Clock Selection 19.2.1. Clock Source Selection 19.2.2. Synchronous Mode 19.2.3. Asynchronous Mode 19.2.4. Programmable Prescaler 19.3. Timer0 Output and Interrupt 19.3.1. Programmable Postscaler 19.3.2. Timer0 Output 19.3.3. Timer0 Interrupt 19.3.4. Timer0 Example 19.4. Operation During Sleep 19.5. Register Summary - Timer0 19.6. Register Definitions: Timer0 Control 19.6.1. T0CON0 19.6.2. T0CON1 19.6.3. TMR0 20. Timer1 Module with Gate Control 20.1. Timer1 Operation 20.2. Clock Source Selection 20.2.1. Internal Clock Source 20.2.2. External Clock Source 20.3. Timer1 Prescaler 20.4. Secondary Oscillator 20.5. Timer1 Operation in Asynchronous Counter Mode 20.5.1. Reading and Writing Timer1 in Asynchronous Counter Mode 20.6. Timer1 16-Bit Read/Write Mode 20.7. Timer1 Gate 20.7.1. Timer1 Gate Enable 20.7.2. Timer1 Gate Source Selection 20.7.3. Timer1 Gate Toggle Mode 20.7.4. Timer1 Gate Single-Pulse Mode 20.7.5. Timer1 Gate Value Status 20.7.6. Timer1 Gate Event Interrupt 20.8. Timer1 Interrupt 20.9. Timer1 Operation During Sleep 20.10. CCP Capture/Compare Time Base 20.11. CCP Special Event Trigger 20.12. Peripheral Module Disable 20.13. Register Summary - Timer1 20.14. Register Definitions: Timer1 20.14.1. TxCON 20.14.2. TxGCON 20.14.3. TMRxCLK 20.14.4. TMRxGATE 20.14.5. TMRx 21. Timer2 Module 21.1. Timer2 Operation 21.1.1. Free Running Period Mode 21.1.2. One-Shot Mode 21.1.3. Monostable Mode 21.2. Timer2 Output 21.3. External Reset Sources 21.4. Timer2 Interrupt 21.5. Operating Modes 21.6. Operation Examples 21.6.1. Software Gate Mode 21.6.2. Hardware Gate Mode 21.6.3. Edge-Triggered Hardware Limit Mode 21.6.4. Level-Triggered Hardware Limit Mode 21.6.5. Software Start One-Shot Mode 21.6.6. Edge-Triggered One-Shot Mode 21.6.7. Edge-Triggered Hardware Limit One-Shot Mode 21.6.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 21.6.9. Edge-Triggered Monostable Modes 21.6.10. Level-Triggered Hardware Limit One-Shot Modes 21.7. Timer2 Operation During Sleep 21.8. Register Summary - Timer2 21.9. Register Definitions: Timer2 Control 21.9.1. TxTMR 21.9.2. TxPR 21.9.3. TxCON 21.9.4. TxHLT 21.9.5. TxCLKCON 21.9.6. TxRST 22. Capture/Compare/PWM Module 22.1. CCP Module Configuration 22.1.1. CCP Modules and Timer Resources 22.1.2. Open-Drain Output Option 22.2. Capture Mode 22.2.1. Capture Sources 22.2.2. Timer1 Mode Resource 22.2.3. Software Interrupt Mode 22.2.4. CCP Prescaler 22.2.5. Capture During Sleep 22.3. Compare Mode 22.3.1. CCPx Pin Configuration 22.3.2. Timer1 Mode Resource 22.3.3. Auto-Conversion Trigger 22.3.4. Compare During Sleep 22.4. PWM Overview 22.4.1. Standard PWM Operation 22.4.2. Setup for PWM Operation 22.4.3. Timer2 Timer Resource 22.4.4. PWM Period 22.4.5. PWM Duty Cycle 22.4.6. PWM Resolution 22.4.7. Operation in Sleep Mode 22.4.8. Changes in System Clock Frequency 22.4.9. Effects of Reset 22.5. Register Summary - CCP Control 22.6. Register Definitions: CCP Control 22.6.1. CCPxCON 22.6.2. CCPxCAP 22.6.3. CCPRx 22.6.4. CCPTMRS0 22.6.5. CCPTMRS1 23. (PWM) Pulse-Width Modulation 23.1. Fundamental Operation 23.2. PWM Output Polarity 23.3. PWM Period 23.4. PWM Duty Cycle 23.5. PWM Resolution 23.6. Operation in Sleep Mode 23.7. Changes in System Clock Frequency 23.8. Effects of Reset 23.9. Setup for PWM Operation using PWMx Output Pins 23.9.1. PWMx Pin Configuration 23.10. Setup for PWM Operation to Other Device Peripherals 23.11. Register Summary - Registers Associated with PWM 23.12. Register Definitions: PWM Control 23.12.1. PWMxCON 23.12.2. CCPTMRS0 23.12.3. CCPTMRS1 23.12.4. PWMxDC 24. (ZCD) Zero-Cross Detection Module 24.1. External Resistor Selection 24.2. ZCD Logic Output 24.3. ZCD Logic Polarity 24.4. ZCD Interrupts 24.5. Correction for ZCPINV Offset 24.5.1. Correction by AC Coupling 24.5.2. Correction By Offset Current 24.6. Handling VPEAK Variations 24.7. Operation During Sleep 24.8. Effects of a Reset 24.9. Disabling the ZCD Module 24.10. Register Summary: ZCD Control 24.11. Register Definitions: ZCD Control 24.11.1. ZCDCON 25. (CWG) Complementary Waveform Generator Module 25.1. Fundamental Operation 25.2. Operating Modes 25.2.1. Half-Bridge Mode 25.2.2. Push-Pull Mode 25.2.3. Full-Bridge Modes 25.2.3.1. Direction Change in Full-Bridge Mode 25.2.3.2. Dead-Band Delay in Full-Bridge Mode 25.2.4. Steering Modes 25.2.4.1. Synchronous Steering Mode 25.2.4.2. Asynchronous Steering Mode 25.3. Start-up Considerations 25.4. Clock Source 25.5. Selectable Input Sources 25.6. Output Control 25.6.1. CWG Outputs 25.6.2. Polarity Control 25.7. Dead-Band Control 25.7.1. Dead-Band Functionality in Half-Bridge mode 25.7.2. Dead-Band Functionality in Full-Bridge mode 25.8. Rising Edge and Reverse Dead Band 25.9. Falling Edge and Forward Dead Band 25.10. Dead-Band Jitter 25.11. Auto-Shutdown 25.11.1. Shutdown 25.11.1.1. Software Generated Shutdown 25.11.1.2. External Input Source 25.11.1.3. Pin Override Levels 25.11.1.4. Auto-Shutdown Interrupts 25.11.2. Auto-Shutdown Restart 25.11.2.1. Software-Controlled Restart 25.11.2.2. Auto-Restart 25.12. Operation During Sleep 25.13. Configuring the CWG 25.14. Register Summary - CWG Control 25.15. Register Definitions: CWG Control 25.15.1. CWGxCON0 25.15.2. CWGxCON1 25.15.3. CWGxCLKCON 25.15.4. CWGxISM 25.15.5. CWGxSTR 25.15.6. CWGxAS0 25.15.7. CWGxAS1 25.15.8. CWGxDBR 25.15.9. CWGxDBF 26. (SMT) Signal Measurement Timer 26.1. SMT Operation 26.1.1. Clock Source Selection 26.1.2. Signal and Window Source Selection 26.1.3. Time Base 26.1.4. Capture Pulse Width and Period Registers 26.1.5. Status Information 26.1.6. Modes of Operation 26.1.6.1. Timer Mode 26.1.6.2. Gated Timer Mode 26.1.6.3. Period and Duty Cycle Measurement Mode 26.1.6.4. High and Low Measurement Mode 26.1.6.5. Windowed Measurement Mode 26.1.6.6. Gated Window Measurement Mode 26.1.6.7. Time of Flight Measurement Mode 26.1.6.8. Capture Mode 26.1.6.9. Counter Mode 26.1.6.10. Gated Counter Mode 26.1.6.11. Windowed Counter Mode 26.1.7. Interrupts 26.1.8. Operation During Sleep 26.2. Register Summary - SMT Control 26.3. Register Definitions: SMT Control 26.3.1. SMTxCON0 26.3.2. SMTxCON1 26.3.3. SMTxSTAT 26.3.4. SMTxCLK 26.3.5. SMTxWIN 26.3.6. SMTxSIG 26.3.7. SMTxTMR 26.3.8. SMTxCPR 26.3.9. SMTxCPW 26.3.10. SMTxPR 27. (DSM) Data Signal Modulator Module 27.1. DSM Operation 27.2. Modulator Signal Sources 27.3. Carrier Signal Sources 27.4. Carrier Synchronization 27.5. Carrier Source Polarity Select 27.6. Programmable Modulator Data 27.7. Modulated Output Polarity 27.8. Operation in Sleep Mode 27.9. Effects of a Reset 27.10. Peripheral Module Disable 27.11. Register Summary - DSM 27.12. Register Definitions: Modulation Control 27.12.1. MDCON0 27.12.2. MDCON1 27.12.3. MDCARH 27.12.4. MDCARL 27.12.5. MDSRC 28. (MSSP) Master Synchronous Serial Port Module 28.1. SPI Mode Overview 28.1.1. SPI Mode Registers 28.2. SPI Mode Operation 28.2.1. SPI Master Mode 28.2.2. SPI Slave Mode 28.2.3. Daisy-Chain Configuration 28.2.4. Slave Select Synchronization 28.2.5. SPI Operation in Sleep Mode 28.3. I2C Mode Overview 28.3.1. Register Definitions: I2C Mode 28.4. I2C Mode Operation 28.4.1. Clock Stretching 28.4.2. Arbitration 28.4.3. Byte Format 28.4.4. Definition of I2C Terminology 28.4.5. SDA and SCL Pins 28.4.6. SDA Hold Time 28.4.7. Start Condition 28.4.8. Stop Condition 28.4.9. Restart Condition 28.4.10. Start/Stop Condition Interrupt Masking 28.4.11. Acknowledge Sequence 28.5. I2C Slave Mode Operation 28.5.1. Slave Mode Addresses 28.5.1.1. I2C Slave 7-bit Addressing Mode 28.5.1.2. I2C Slave 10-bit Addressing Mode 28.5.2. Slave Reception 28.5.2.1. 7-bit Addressing Reception 28.5.2.2. 7-bit Reception with AHEN and DHEN 28.5.3. Slave Transmission 28.5.3.1. Slave Mode Bus Collision 28.5.3.2. 7-bit Transmission 28.5.3.3. 7-bit Transmission with Address Hold Enabled 28.5.4. Slave Mode 10-bit Address Reception 28.5.5. 10-bit Addressing with Address or Data Hold 28.5.6. Clock Stretching 28.5.6.1. Normal Clock Stretching 28.5.6.2. 10-bit Addressing Mode 28.5.6.3. Byte NACKing 28.5.7. Clock Synchronization and the CKP bit 28.5.8. General Call Address Support 28.5.9. SSP Mask Register 28.6. I2C Master Mode 28.6.1. I2C Master Mode Operation 28.6.2. Clock Arbitration 28.6.3. WCOL Status Flag 28.6.4. I2C Master Mode Start Condition Timing 28.6.5. I2C Master Mode Repeated Start Condition Timing 28.6.6. I2C Master Mode Transmission 28.6.6.1. BF Status Flag 28.6.6.2. WCOL Status Flag 28.6.6.3. ACKSTAT Status Flag 28.6.6.4. Typical transmit sequence: 28.6.7. I2C Master Mode Reception 28.6.7.1. BF Status Flag 28.6.7.2. SSPOV Status Flag 28.6.7.3. WCOL Status Flag 28.6.7.4. Typical Receive Sequence: 28.6.8. Acknowledge Sequence Timing 28.6.8.1. Acknowledge Write Collision 28.6.9. Stop Condition Timing 28.6.9.1. Write Collision on Stop 28.6.10. Sleep Operation 28.6.11. Effects of a Reset 28.6.12. Multi-Master Mode 28.6.13. Multi -Master Communication, Bus Collision and Bus Arbitration 28.6.13.1. Bus Collision During a Start Condition 28.6.13.2. Bus Collision During a Repeated Start Condition 28.6.13.3. Bus Collision During a Stop Condition 28.7. Baud Rate Generator 28.8. Register Summary: MSSP Control 28.9. Register Definitions: MSSP Control 28.9.1. SSPxSTAT 28.9.2. SSPxCON1 28.9.3. SSPxCON2 28.9.4. SSPxCON3 28.9.5. SSPxBUF 28.9.6. SSPxADD 28.9.7. SSPxMSK 29. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter 29.1. EUSART Asynchronous Mode 29.1.1. EUSART Asynchronous Transmitter 29.1.1.1. Enabling the Transmitter 29.1.1.2. Transmitting Data 29.1.1.3. Transmit Data Polarity 29.1.1.4. Transmit Interrupt Flag 29.1.1.5. TSR Status 29.1.1.6. Transmitting 9-Bit Characters 29.1.1.7. Asynchronous Transmission Setup 29.1.2. EUSART Asynchronous Receiver 29.1.2.1. Enabling the Receiver 29.1.2.2. Receiving Data 29.1.2.3. Receive Interrupts 29.1.2.4. Receive Framing Error 29.1.2.5. Receive Overrun Error 29.1.2.6. Receiving 9-Bit Characters 29.1.2.7. Address Detection 29.1.2.8. Asynchronous Reception Setup 29.1.2.9. 9-Bit Address Detection Mode Setup 29.1.3. Clock Accuracy with Asynchronous Operation 29.2. EUSART Baud Rate Generator (BRG) 29.2.1. Auto-Baud Detect 29.2.2. Auto-Baud Overflow 29.2.3. Auto-Wake-up on Break 29.2.3.1. Special Considerations 29.2.4. Break Character Sequence 29.2.4.1. Break and Sync Transmit Sequence 29.2.5. Receiving a Break Character 29.3. EUSART Synchronous Mode 29.3.1. Synchronous Master Mode 29.3.1.1. Master Clock 29.3.1.2. Clock Polarity 29.3.1.3. Synchronous Master Transmission 29.3.1.4. Synchronous Master Transmission Setup 29.3.1.5. Synchronous Master Reception 29.3.1.6. Receive Overrun Error 29.3.1.7. Receiving 9-Bit Characters 29.3.1.8. Synchronous Master Reception Setup 29.3.2. Synchronous Slave Mode 29.3.2.1. Slave Clock 29.3.2.2. EUSART Synchronous Slave Transmit 29.3.2.3. Synchronous Slave Transmission Setup 29.3.2.4. EUSART Synchronous Slave Reception 29.3.2.5. Synchronous Slave Reception Setup: 29.4. EUSART Operation During Sleep 29.4.1. Synchronous Receive During Sleep 29.4.2. Synchronous Transmit During Sleep 29.5. Register Summary - EUSART 29.6. Register Definitions: EUSART Control 29.6.1. RCxSTA 29.6.2. TXxSTA 29.6.3. BAUDxCON 29.6.4. SPxBRG 29.6.5. RCxREG 29.6.6. TXxREG 30. (FVR) Fixed Voltage Reference 30.1. Independent Gain Amplifiers 30.2. FVR Stabilization Period 30.3. Register Summary - FVR 30.4. Register Definitions: FVR Control 30.4.1. FVRCON 31. Temperature Indicator Module 31.1. Circuit Operation 31.2. Minimum Operating VDD 31.3. Temperature Output 31.4. ADC Acquisition Time 32. (DAC) 5-Bit Digital-to-Analog Converter Module 32.1. Output Voltage Selection 32.2. Ratiometric Output Level 32.3. DAC Voltage Reference Output 32.4. Operation During Sleep 32.5. Effects of a Reset 32.6. Register Summary - DAC Control 32.7. Register Definitions: DAC Control 32.7.1. DAC1CON0 32.7.2. DAC1CON1 33. (ADC2) Analog-to-Digital Converter with Computation Module 33.1. ADC Configuration 33.1.1. Port Configuration 33.1.2. Channel Selection 33.1.3. ADC Voltage Reference 33.1.4. Conversion Clock 33.1.5. Interrupts 33.1.6. Result Formatting 33.2. ADC Operation 33.2.1. Starting a Conversion 33.2.2. Completion of a Conversion 33.2.3. Terminating a Conversion 33.2.4. ADC Operation During Sleep 33.2.5. External Trigger During Sleep 33.2.6. Auto-Conversion Trigger 33.2.7. ADC Conversion Procedure (Basic Mode) 33.3. ADC Acquisition Requirements 33.4. Capacitive Voltage Divider (CVD) Features 33.4.1. CVD Operation 33.4.2. PreCharge Control 33.4.3. Acquisition Control for CVD (ADPRE > 0) 33.4.4. Guard Ring Outputs 33.4.5. Additional Sample and Hold Capacitance 33.5. Computation Operation 33.5.1. Digital Filter/Average 33.5.2. Basic Mode 33.5.3. Accumulate Mode 33.5.4. Average Mode 33.5.5. Burst Average Mode 33.5.6. Low-pass Filter Mode 33.5.7. Threshold Comparison 33.5.8. Continuous Sampling Mode 33.5.9. Double Sample Conversion 33.6. Register Summary - ADC Control 33.7. Register Definitions: ADC Control 33.7.1. ADCON0 33.7.2. ADCON1 33.7.3. ADCON2 33.7.4. ADCON3 33.7.5. ADSTAT 33.7.6. ADCLK 33.7.7. ADREF 33.7.8. ADPCH 33.7.9. ADPRE 33.7.10. ADACQ 33.7.11. ADCAP 33.7.12. ADRPT 33.7.13. ADCNT 33.7.14. ADFLTR 33.7.15. ADRES 33.7.16. ADPREV 33.7.17. ADACC 33.7.18. ADSTPT 33.7.19. ADERR 33.7.20. ADLTH 33.7.21. ADUTH 33.7.22. ADACT 34. (CMP) Comparator Module 34.1. Comparator Overview 34.2. Comparator Control 34.2.1. Comparator Enable 34.2.2. Comparator Output 34.2.3. Comparator Output Polarity 34.3. Comparator Hysteresis 34.4. Operation With Timer1 Gate 34.4.1. Comparator Output Synchronization 34.5. Comparator Interrupt 34.6. Comparator Positive Input Selection 34.7. Comparator Negative Input Selection 34.8. Comparator Response Time 34.9. Analog Input Connection Considerations 34.10. CWG1 Auto-Shutdown Source 34.11. ADC Auto-Trigger Source 34.12. Even Numbered Timers Reset 34.13. Operation in Sleep Mode 34.14. Register Summary - Comparator 34.15. Register Definitions: Comparator Control 34.15.1. CMxCON0 34.15.2. CMxCON1 34.15.3. CMxNCH 34.15.4. CMxPCH 34.15.5. CMOUT 35. (HLVD) High/Low-Voltage Detect 35.1. Operation 35.2. Setup 35.3. Current Consumption 35.4. HLVD Start-up Time 35.5. Applications 35.6. Operation During Sleep 35.7. Operation During Idle and Doze Modes 35.8. Effects of a Reset 35.9. Register Summary - HLVD 35.10. Register Definitions: HLVD Control 35.10.1. HLVDCON0 35.10.2. HLVDCON1 36. Register Summary 37. In-Circuit Serial Programming™ (ICSP™) 37.1. High-Voltage Programming Entry Mode 37.2. Low-Voltage Programming Entry Mode 37.3. Common Programming Interfaces 38. Instruction Set Summary 38.1. Standard Instruction Set 38.1.1. Standard Instruction Set 38.2. Extended Instruction Set 38.2.1. Extended Instruction Syntax 38.2.2. Extended Instruction Set 38.2.3. Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode 38.2.3.1. Extended Instruction Syntax with Standard PIC18 Commands 38.2.4. Considerations when Enabling the Extended Instruction Set 38.2.5. Special Considerations with Microchip MPLAB® IDE Tools 39. Development Support 39.1. MPLAB X Integrated Development Environment Software 39.2. MPLAB XC Compilers 39.3. MPASM Assembler 39.4. MPLINK Object Linker/MPLIB Object Librarian 39.5. MPLAB Assembler, Linker and Librarian for Various Device Families 39.6. MPLAB X SIM Software Simulator 39.7. MPLAB REAL ICE In-Circuit Emulator System 39.8. MPLAB ICD 3 In-Circuit Debugger System 39.9. PICkit 3 In-Circuit Debugger/Programmer 39.10. MPLAB PM3 Device Programmer 39.11. Demonstration/Development Boards, Evaluation Kits, and Starter Kits 39.12. Third-Party Development Tools 40. Electrical Specifications 40.1. Absolute Maximum Ratings(†) 40.2. Standard Operating Conditions 40.3. DC Characteristics 40.3.1. Supply Voltage 40.3.2. Supply Current (IDD)(1,2,4) 40.3.3. Power-Down Current (IPD)(1,2) 40.3.4. I/O Ports 40.3.5. Memory Programming Specifications 40.3.6. Thermal Characteristics 40.4. AC Characteristics 40.4.1. External Clock/Oscillator Timing Requirements 40.4.2. Internal Oscillator Parameters(1) 40.4.3. PLL Specifications 40.4.4. I/O and CLKOUT Timing Specifications 40.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 40.4.6. High/Low-Voltage Detect Characteristics 40.4.7. Analog-To-Digital Converter (ADC) Accuracy Specifications(1,2) 40.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 40.4.9. Comparator Specifications 40.4.10. 5-Bit DAC Specifications 40.4.11. Fixed Voltage Reference (FVR) Specifications 40.4.12. Zero Cross Detect (ZCD) Specifications 40.4.13. Timer0 and Timer1 External Clock Requirements 40.4.14. Capture/Compare/PWM Requirements (CCP) 40.4.15. EUSART Synchronous Transmission Requirements 40.4.16. EUSART Synchronous Receive Requirements 40.4.17. SPI Mode Requirements 40.4.18. I2C Bus Start/Stop Bits Requirements 40.4.19. I2C Bus Data Requirements 41. DC and AC Characteristics Graphs and Tables 41.1. Graphs 42. Packaging Information 42.1. Package Details 43. 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