Datasheet ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P (Microchip)

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Atmel ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash DATASHEET Features
• High performance, low power Atmel® AVR® 8-Bit Microcontroller • Advanced RISC architecture – 130 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 16MIPS throughput at16MHz (Atmel ATmega169A/169PA/649A/649P) – Up to 20 MIPS throughput at 20MHz (Atmel ATmega329A/329PA/3290A/3290PA/6490A/6490P) – On-chip 2-cycle multiplier • High endurance non-volatile memory segments – In-system self-programmable flash program memory • 16Kbytes (Atmel ATmega169A/ATmega169PA) • 32Kbytes (Atmel ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA) • 64Kbytes (Atmel ATmega649A/ATmega649P/ATmega6490A/ATmega6490P) – EEPROM • 512bytes (ATmega169A/ATmega169PA) • 1Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA) • 2Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P) – Internal SRAM • 1Kbytes (ATmega169A/ATmega169PA) • 2Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA) • 4Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P) – Write/erase cyles: 10,000 flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True read-while-write operation – Programming lock for software security • Atmel QTouch® library support – Capacitive touch buttons, sliders and wheels – Atmel QTouch and QMatrix acquisition – Up to 64 sense channels • JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan capabilities according to the JTAG standard – Extensive on-chip debug support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral features – 4 × 25 segment LCD driver (ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P) – 4 × 40 segment LCD driver (ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P) – Two 8-bit Timer/Counters with Separate Prescaler and Compare mode – One 16-bit Timer/Counter with Separate Prescaler, Compare mode, and Capture mode – Real Time Counter with separate oscillator 8284F–AVR–07/2014 Document Outline Features 1. Pin configurations 1.1 Pinout - 64A (TQFP) and 64M1 (QFN/MLF) 1.2 Pinout - 100A (TQFP) 1.3 Pinout - 64MC (DRQFN) 2. Overview 2.1 Block diagram 2.2 Comparison between Atmel ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P 2.3 Pin descriptions 2.3.1 VCC 2.3.2 GND 2.3.3 Port A (PA7...PA0) 2.3.4 Port B (PB7...PB0) 2.3.5 Port C (PC7...PC0) 2.3.6 Port D (PD7...PD0) 2.3.7 Port E (PE7...PE0) 2.3.8 Port F (PF7...PF0) 2.3.9 Port G (PG5...PG0) 2.3.10 Port H (PH7...PH0) 2.3.11 Port J (PJ6...PJ0) 2.3.12 RESET 2.3.13 XTAL1 2.3.14 XTAL2 2.3.15 AVCC 2.3.16 AREF 2.3.17 LCDCAP 3. Resources 4. Data retention 5. About code examples 6. Capacitive touch sensing 7. AVR CPU core 7.1 Overview 7.2 Architectural overview 7.3 ALU – Arithmetic Logic Unit 7.4 AVR Status Register 7.4.1 SREG – AVR Status Register 7.5 General Purpose Register File 7.5.1 The X-register, Y-register and Z-register 7.6 Stack pointer 7.6.1 SPH and SPL – Stack pointer High and Stack Pointer Low 7.7 Instruction execution timing 7.8 Reset and interrupt handling 7.8.1 Interrupt response time 8. AVR memories 8.1 In-system reprogrammable flash program memory 8.2 SRAM data memory 8.2.1 Data memory access times 8.3 EEPROM data memory 8.3.1 EEPROM read/write access 8.3.2 EEPROM write during Power-down Sleep mode 8.3.3 Preventing EEPROM corruption 8.4 I/O memory 8.5 General purpose I/O registers 8.6 Register description 8.6.1 EEARH and EEARL – EEPROM address register Atmel ATmega169A/169PA 8.6.2 EEARH and EEARL – EEPROM address register Atmel ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P 8.6.3 EEDR – EEPROM data register 8.6.4 EECR – EEPROM control register 8.6.5 GPIOR2 – General Purpose I/O Register 2 8.6.6 GPIOR1 – General Purpose I/O Register 1 8.6.7 GPIOR0 – General Purpose I/O Register 0 9. System clock and clock options 9.1 Clock systems and their distribution 9.1.1 CPU Clock – clkCPU 9.1.2 I/O Clock – clkI/O 9.1.3 Flash Clock – clkFLASH 9.1.4 Asynchronous Timer Clock – clkASY 9.1.5 ADC Clock – clkADC 9.2 Clock sources 9.3 Default clock source 9.4 Calibrated internal RC oscillator 9.5 XTAL oscillator 9.6 Low-frequency XTAL oscillator 9.7 External clock 9.8 Clock Output Buffer 9.9 Timer/Counter Oscillator 9.10 System Clock Prescaler 9.10.1 Switching Time 9.11 Register Description 9.11.1 OSCCAL – Oscillator Calibration Register 9.11.2 CLKPR – Clock Prescale Register 10. Power management and sleep modes 10.1 Overview 10.2 Sleep modes 10.3 BOD disable (1) 10.4 Idle mode 10.5 ADC Noise Reduction mode 10.6 Power-down mode 10.7 Power-save mode 10.8 Standby mode 10.9 Power Reduction Register 10.10 Minimizing power consumption 10.10.1 Analog to Digital Converter 10.10.2 Analog Comparator 10.10.3 Brown-out Detector 10.10.4 Internal Voltage Reference 10.10.5 Watchdog Timer 10.10.6 Port pins 10.10.7 JTAG interface and On-chip Debug System 10.11 Register description 10.11.1 SMCR – Sleep Mode Control Register 10.11.2 MCUCR – MCU Control Register 10.11.3 PRR – Power Reduction Register 11. System control and reset 11.1 Resetting the AVR 11.2 Reset sources 11.2.1 Power-on Reset 11.2.2 External Reset 11.2.3 Brown-out detection 11.2.4 Watchdog reset 11.3 Internal voltage reference 11.3.1 Voltage reference enable signals and start-up time 11.4 Watchdog Timer 11.4.1 Timed sequences for changing the configuration of the Watchdog Timer 11.4.2 Safety Level 1 11.4.3 Safety Level 2 11.5 Register description 11.5.1 MCUSR – MCU Status Register 11.5.2 WDTCR – Watchdog Timer Control Register 12. Interrupts 12.1 Overview 12.2 Interrupt vectors 12.2.1 Moving interrupts between application and boot space 12.3 Register description 12.3.1 MCUCR – MCU Control Register 13. External interrupts 13.1 Overview 13.2 Pin change interrupt timing 13.3 Register description 13.3.1 EICRA – External Interrupt Control Register A 13.3.2 EIMSK – External Interrupt Mask Register 13.3.3 EIFR – External Interrupt Flag Register 13.3.4 PCMSK3 – Pin Change Mask Register 3 (1) 13.3.5 PCMSK2 – Pin Change Mask Register 2 (1) 13.3.6 PCMSK1 – Pin Change Mask Register 1 13.3.7 PCMSK0 – Pin Change Mask Register 0 14. I/O-ports 14.1 Overview 14.2 Ports as general digital I/O 14.2.1 Configuring the pin 14.2.2 Toggling the pin 14.2.3 Switching between input and output 14.2.4 Reading the pin value 14.2.5 Digital Input Enable and Sleep Modes 14.2.6 Unconnected pins 14.3 Alternate port functions 14.3.1 Alternate functions of Port A 14.3.2 Alternate functions of Port B 14.3.3 Alternate functions of Port C 14.3.4 Alternate functions of Port D 14.3.5 Alternate functions of Port E 14.3.6 Alternate functions of Port F 14.3.7 Alternate Functions of Port G 14.3.8 Alternate Functions of Port H 14.3.9 Alternate Functions of Port J 14.4 Register description 14.4.1 MCUCR – MCU Control Register 14.4.2 PORTA – Port A Data Register 14.4.3 DDRA – Port A Data Direction Register 14.4.4 PINA – Port A Input Pins Address 14.4.5 PORTB – Port B Data Register 14.4.6 DDRB – Port B Data Direction Register 14.4.7 PINB – Port B Input Pins Address 14.4.8 PORTC – Port C Data Register 14.4.9 DDRC – Port C Data Direction Register 14.4.10 PINC – Port C Input Pins Address 14.4.11 PORTD – Port D Data Register 14.4.12 DDRD – Port D Data Direction Register 14.4.13 PIND – Port D Input Pins Address 14.4.14 PORTE – Port E Data Register 14.4.15 DDRE – Port E Data Direction Register 14.4.16 PINE – Port E Input Pins Address 14.4.17 PORTF – Port F Data Register 14.4.18 DDRF – Port F Data Direction Register 14.4.19 PINF – Port F Input Pins Address 14.4.20 PORTG – Port G Data Register 14.4.21 DDRG – Port G Data Direction Register 14.4.22 PING – Port G Input Pins Address 14.4.23 PORTH – Port H Data Register (1) 14.4.24 DDRH – Port H Data Direction Register (1) 14.4.25 PINH – Port H Input Pins Address (1) 14.4.26 PORTJ – Port J Data Register (1) 14.4.27 DDRJ – Port J Data Direction Register (1) 14.4.28 PINJ – Port J Input Pins Address (1) 15. 8-bit Timer/Counter0 with PWM 15.1 Features 15.2 Overview 15.2.1 Registers 15.2.2 Definitions 15.3 Timer/Counter Clock Sources 15.4 Counter Unit 15.5 Output Compare Unit 15.5.1 Force Output Compare 15.5.2 Compare Match Blocking by TCNT0 Write 15.5.3 Using the Output Compare Unit 15.6 Compare Match Output Unit 15.6.1 Compare Output Mode and Waveform Generation 15.7 Modes of Operation 15.7.1 Normal Mode 15.7.2 Clear Timer on Compare Match (CTC) Mode 15.7.3 Fast PWM Mode 15.7.4 Phase Correct PWM Mode 15.8 Timer/Counter Timing Diagrams 15.9 Register description 15.9.1 TCCR0A – Timer/Counter Control Register A 15.9.2 TCNT0 – Timer/Counter Register 15.9.3 OCR0A – Output Compare Register A 15.9.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register 15.9.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register 16. 16-bit Timer/Counter1 16.1 Features 16.2 Overview 16.2.1 Registers 16.2.2 Definitions 16.2.3 Compatibility 16.3 Accessing 16-bit registers 16.3.1 Reusing the Temporary High Byte Register 16.4 Timer/Counter Clock Sources 16.5 Counter Unit 16.6 Input Capture Unit 16.6.1 Input Capture Trigger Source 16.6.2 Noise Canceler 16.6.3 Using the Input Capture Unit 16.7 Output Compare Units 16.7.1 Force Output Compare 16.7.2 Compare Match Blocking by TCNT1 Write 16.7.3 Using the Output Compare Unit 16.8 Compare Match Output Unit 16.8.1 Compare Output Mode and Waveform Generation 16.9 Modes of Operation 16.9.1 Normal Mode 16.9.2 Clear Timer on Compare Match (CTC) Mode 16.9.3 Fast PWM Mode 16.9.4 Phase Correct PWM Mode 16.9.5 Phase and Frequency Correct PWM Mode 16.10 Timer/Counter timing diagrams 16.11 Register description 16.11.1 TCCR1A – Timer/Counter1 Control Register A 16.11.2 TCCR1B – Timer/Counter1 Control Register B 16.11.3 TCCR1C – Timer/Counter1 Control Register C 16.11.4 TCNT1H and TCNT1L – Timer/Counter1 16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 16.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B 16.11.7 ICR1H and ICR1L – Input Capture Register 1 16.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register 17. Timer/Counter0 and Timer/Counter1 Prescalers 17.1 Internal Clock Source 17.2 Prescaler Reset 17.3 External Clock Source 17.4 Register description 17.4.1 TCCR0A – Timer/Counter Control Register A 17.4.2 TCNT0 – Timer/Counter Register 17.4.3 OCR0A – Output Compare Register A 17.4.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register 17.4.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register 17.4.6 GTCCR – General Timer/Counter Control Register 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features 18.2 Overview 18.2.1 Registers 18.2.2 Definitions 18.3 Timer/Counter clock sources 18.4 Counter Unit 18.5 Output Compare Unit 18.5.1 Force Output Compare 18.5.2 Compare Match Blocking by TCNT2 Write 18.5.3 Using the Output Compare Unit 18.6 Compare Match Output Unit 18.6.1 Compare Output Mode and Waveform Generation 18.7 Modes of Operation 18.7.1 Normal Mode 18.7.2 Clear Timer on Compare Match (CTC) Mode 18.7.3 Fast PWM Mode 18.7.4 Phase Correct PWM Mode 18.8 Timer/Counter timing diagrams 18.9 Asynchronous operation of Timer/Counter2 18.9.1 Timer/Counter prescaler 18.10 Register Description 18.10.1 TCCR2A – Timer/Counter Control Register A 18.10.2 TCNT2 – Timer/Counter Register 18.10.3 OCR2A – Output Compare Register A 18.10.4 ASSR – Asynchronous Status Register 18.10.5 TIMSK2 – Timer/Counter2 Interrupt Mask Register 18.10.6 TIFR2 – Timer/Counter2 Interrupt Flag Register 18.10.7 GTCCR – General Timer/Counter Control Register 19. SPI – Serial Peripheral Interface 19.1 Features 19.2 Overview 19.3 SS pin functionality 19.3.1 Slave Mode 19.3.2 Master Mode 19.4 Data modes 19.5 Register description 19.5.1 SPCR – SPI Control Register 19.5.2 SPSR – SPI Status Register 19.5.3 SPDR – SPI Data Register 20. USART0 20.1 Features 20.2 Overview 20.2.1 AVR USART vs. AVR UART – Compatibility 20.3 Clock Generation 20.3.1 Internal Clock Generation – The Baud Rate Generator 20.3.2 Double Speed Operation (U2Xn) 20.3.3 External Clock 20.3.4 Synchronous Clock Operation 20.4 Frame formats 20.4.1 Parity Bit Calculation 20.5 USART initialization 20.6 Data transmission – the USART transmitter 20.6.1 Sending frames with 5 to 8 data bit 20.6.2 Sending frames with 9 data bit 20.6.3 Transmitter Flags and Interrupts 20.6.4 Parity Generator 20.6.5 Disabling the Transmitter 20.7 Data reception – the USART receiver 20.7.1 Receiving frames with 5 to 8 data bits 20.7.2 Receiving frames with 9 data bits 20.7.3 Receive Compete Flag and Interrupt 20.7.4 Receiver Error Flags 20.7.5 Parity Checker 20.7.6 Disabling the Receiver 20.7.7 Flushing the Receive Buffer 20.8 Asynchronous data reception 20.8.1 Asynchronous Clock Recovery 20.8.2 Asynchronous Data Recovery 20.8.3 Asynchronous Operational Range 20.9 Multi-processor Communication Mode 20.9.1 Using MPCM 20.10 Examples of Baud Rate Setting 20.11 Register description 20.11.1 UDRn – USART I/O Data Register n 20.11.2 UCSRnA – USART Control and Status Register n A 20.11.3 UCSRnB – USART Control and Status Register n B 20.11.4 UCSRnC – USART Control and Status Register n C 20.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers n 21. USI – Universal Serial Interface 21.1 Features 21.2 Overview 21.3 Functional descriptions 21.3.1 Three-wire Mode 21.3.2 SPI Master Operation Example 21.3.3 SPI Slave Operation Example 21.3.4 Two-wire Mode 21.3.5 Start Condition Detector 21.3.6 Clock speed considerations 21.4 Alternative USI Usage 21.4.1 Half-duplex Asynchronous Data Transfer 21.4.2 4-bit Counter 21.4.3 12-bit Timer/Counter 21.4.4 Edge Triggered External Interrupt 21.4.5 Software Interrupt 21.5 Register description 21.5.1 USIDR – USI Data Register 21.5.2 USISR – USI Status Register 21.5.3 USICR – USI Control Register 22. Analog Comparator 22.1 Overview 22.2 Analog Comparator Multiplexed Input 22.3 Register description 22.3.1 ADCSRB – ADC Control and Status Register B 22.3.2 ACSR – Analog Comparator Control and Status Register 22.3.3 DIDR1 – Digital Input Disable Register 1 23. Analog to Digital Converter 23.1 Features 23.2 Overview 23.3 Operation 23.4 Starting a Conversion 23.5 Prescaling and Conversion Timing 23.6 Changing Channel or Reference Selection 23.6.1 ADC Input Channels 23.6.2 ADC Voltage Reference 23.7 ADC Noise Canceler 23.7.1 Analog Input Circuitry 23.7.2 Analog Noise Canceling Techniques 23.7.3 ADC Accuracy Definitions 23.8 ADC Conversion Result 23.9 Register description 23.9.1 ADMUX – ADC Multiplexer Selection Register 23.9.2 ADCSRA – ADC Control and Status Register A 23.9.3 ADCL and ADCH – The ADC Data Register 23.9.3.1 ADLAR = 0 23.9.3.2 ADLAR = 1 23.9.4 ADCSRB – ADC Control and Status Register B 23.9.5 DIDR0 – Digital Input Disable Register 0 24. LCD Controller 24.1 Features 24.2 Overview 24.2.1 Definitions 24.2.2 LCD Clock Sources 24.2.3 LCD Prescaler 24.2.4 LCD Memory 24.2.5 LCD Contrast Controller/Power Supply 24.2.6 LCDCAP 24.2.7 LCD Buffer Driver 24.2.8 Display requirements 24.2.9 Minimizing power consumption 24.3 Mode of operation 24.3.1 Static Duty and Bias 24.3.2 1/2 Duty and 1/2 Bias 24.3.3 1/3 Duty and 1/3 Bias 24.3.4 1/4 Duty and 1/3 Bias 24.3.5 Low Power Waveform 24.3.6 Operation in Sleep Mode 24.3.7 Display Blanking 24.3.8 Port Mask 24.4 LCD Usage 24.4.1 LCD Initialization 24.4.2 Updating the LCD 24.4.3 Disabling the LCD 24.5 Register description 24.5.1 LCDCRA – LCD Control and Status Register A 24.5.2 LCDCRB – LCD Control and Status Register B 24.5.3 LCDFRR – LCD Frame Rate Register 24.5.4 LCDCCR – LCD Contrast Control Register 24.5.5 LCD Memory Mapping 25. JTAG Interface and On-chip Debug System 25.1 Features 25.2 Overview 25.3 TAP – Test Access Port 25.4 TAP Controller 25.5 Using the Boundary-scan chain 25.6 Using the On-chip Debug System 25.7 On-chip Debug specific JTAG instructions 25.7.1 PRIVATE0; 0x8 25.7.2 PRIVATE1; 0x9 25.7.3 PRIVATE2; 0xA 25.7.4 PRIVATE3; 0xB 25.8 Using the JTAG Programming Capabilities 25.9 Bibliography 25.10 Register description 25.10.1 OCDR – On-chip Debug Register 26. IEEE 1149.1 (JTAG) Boundary-scan 26.1 Features 26.2 Overview 26.3 Data registers 26.3.1 Bypass Register 26.3.2 Device Identification Register 26.3.2.1 Version 26.3.2.2 Part Number 26.3.2.3 Manufacturer ID 26.3.3 Reset Register 26.3.4 Boundary-scan Chain 26.4 Boundary-scan specific JTAG instructions 26.4.1 EXTEST; 0x0 26.4.2 IDCODE; 0x1 26.4.3 SAMPLE_PRELOAD; 0x2 26.4.4 AVR_RESET; 0xC 26.4.5 BYPASS; 0xF 26.5 Boundary-scan Chain 26.5.1 Scanning the Digital Port Pins 26.5.2 Scanning the RESET pin 26.5.3 Scanning the Clock pins 26.5.4 Scanning the Analog Comparator 26.5.5 Scanning the ADC 26.6 Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P Boundary-scan order 26.7 Boundary-scan Description Language Files 26.8 Register description 26.8.1 MCUCR – MCU Control Register 26.8.2 MCUSR – MCU Status Register 27. Boot Loader Support – Read-While-Write Self-Programming 27.1 Features 27.2 Overview 27.3 Application and Boot Loader Flash Sections 27.3.1 Application Section 27.3.2 BLS – Boot Loader Section 27.4 Read-While-Write and No Read-While-Write Flash Sections 27.4.1 RWW – Read-While-Write Section 27.4.2 NRWW – No Read-While-Write Section 27.5 Boot Loader Lock Bits 27.6 Entering the Boot Loader Program 27.7 Addressing the Flash During Self-Programming 27.8 Self-Programming the Flash 27.8.1 Performing Page Erase by SPM 27.8.2 Filling the Temporary Buffer (Page Loading) 27.8.3 Performing a Page Write 27.8.4 Using the SPM Interrupt 27.8.5 Consideration While Updating BLS 27.8.6 Prevent Reading the RWW Section During Self-Programming 27.8.7 Setting the Boot Loader Lock Bits by SPM 27.8.8 EEPROM Write Prevents Writing to SPMCSR 27.8.9 Reading the Fuse and Lock Bits from Software 27.8.10 Preventing Flash Corruption 27.8.11 Programming Time for Flash when Using SPM 27.8.12 Simple Assembly Code Example for a Boot Loader 27.8.13 Boot Loader Parameters 27.8.13.1 Atmel ATmega169A/169PA 27.8.13.2 Atmel ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P 27.9 Register description 27.9.1 SPMCSR – Store Program Memory Control and Status Register 28. Memory programming 28.1 Program and Data Memory Lock Bits 28.2 Fuse bits 28.2.1 Latching of Fuses 28.3 Signature Bytes 28.4 Calibration Byte 28.5 Page size 28.6 Parallel Programming Parameters, Pin Mapping, and Commands 28.6.1 Signal Names 28.7 Parallel programming 28.7.1 Enter programming mode 28.7.2 Considerations for Efficient Programming 28.7.3 Chip Erase 28.7.4 Programming the Flash 28.7.5 Programming the EEPROM 28.7.6 Reading the Flash 28.7.7 Reading the EEPROM 28.7.8 Programming the Fuse Low Bits 28.7.9 Programming the Fuse High Bits 28.7.10 Programming the Extended Fuse Bits 28.7.11 Programming the Lock Bits 28.7.12 Reading the Fuse and Lock Bits 28.7.13 Reading the Signature Bytes 28.7.14 Reading the Calibration Byte 28.7.15 Parallel Programming Characteristics 28.8 Serial downloading 28.8.1 Serial programming pin mapping 28.8.2 Serial Programming Algorithm 28.8.3 Serial programming instruction set 28.8.4 SPI Serial Programming Characteristics 28.9 Programming via the JTAG Interface 28.9.1 Programming Specific JTAG Instructions 28.9.2 AVR_RESET (0xC) 28.9.3 PROG_ENABLE (0x4) 28.9.4 PROG_COMMANDS (0x5) 28.9.5 PROG_PAGELOAD (0x6) 28.9.6 PROG_PAGEREAD (0x7) 28.9.7 Data Registers 28.9.8 Reset Register 28.9.9 Programming Enable Register 28.9.10 Programming Command Register 28.9.11 Flash Data Byte Register 28.9.12 Programming Algorithm 28.9.13 Entering Programming Mode 28.9.14 Leaving Programming Mode 28.9.15 Performing Chip Erase 28.9.16 Programming the Flash 28.9.17 Reading the Flash 28.9.18 Programming the EEPROM 28.9.19 Reading the EEPROM 28.9.20 Programming the Fuses 28.9.21 Programming the Lock Bits 28.9.22 Reading the Fuses and Lock Bits 28.9.23 Reading the Signature Bytes 28.9.24 Reading the Calibration Byte 29. Electrical characteristics – TA = -40°C to 85°C 29.1 Absolute maximum ratings* 29.2 DC Characteristics 29.2.1 ATmega169A DC Characteristics 29.2.2 ATmega169PA DC Characteristics 29.2.3 ATmega329A DC Characteristics 29.2.4 ATmega329PA DC Characteristics 29.2.5 ATmega3290A DC Characteristics 29.2.6 ATmega3290PA DC Characteristics 29.2.7 ATmega649A DC Characteristics 29.2.8 ATmega649P DC Characteristics 29.2.9 ATmega6490A DC Characteristics 29.2.10 ATmega6490P DC Characteristics 29.3 Speed Grades 29.4 Clock characteristics 29.4.1 Calibrated internal RC oscillator accuracy 29.4.2 External clock drive waveforms 29.4.3 External clock drive 29.5 System and reset characteristics 29.6 Brown-out Detection 29.7 External Interrupts Characteristics 29.8 SPI Timing Characteristics 29.9 ADC characteristics 29.10 LCD controller characteristics 30. Electrical Characteristics – TA = -40°C to 105°C 30.1 Absolute Maximum Ratings* 30.2 DC Characteristics 30.2.1 Current consumption ATmega169PA 30.2.2 Current consumption ATmega329A 30.2.3 Current consumption ATmega329P 30.2.4 Current consumption ATmega329PA 30.2.5 Current consumption ATmega3290A 30.2.6 Current consumption ATmega3290P 30.2.7 Current consumption ATmega3290PA 31. Typical Characteristics – TA = -40°C to 85°C 31.1 Atmel ATmega169A 31.1.1 Active Supply Current 31.1.2 Idle supply current 31.1.3 ATmega169A: Supply current of I/O modules 31.1.3.1 Example 1 31.1.4 Power-down supply current 31.1.5 Power-save supply current 31.1.6 Standby supply current 31.1.7 Pin pull-up 31.1.8 Pin driver strength 31.1.9 Pin Threshold and Hysteresis 31.1.10 BOD Thresholds and Analog Comparator offset 31.1.11 Internal oscillator speed 31.1.12 Current consumption of peripheral units 31.1.13 Current consumption in Reset and Reset Pulswidth 31.2 Atmel ATmega169PA 31.2.1 Active supply current 31.2.2 Idle supply current 31.2.3 Atmel ATmega169PA: Supply current of I/O modules 31.2.3.1 Example 1 31.2.4 Power-down supply current 31.2.5 Power-save supply current 31.2.6 Standby supply current 31.2.7 Pin pull-up 31.2.8 Pin driver strength 31.2.9 Pin Threshold and Hysteresis 31.2.10 BOD Thresholds and Analog Comparator offset 31.2.11 Internal oscillator speed 31.2.12 Current consumption of peripheral units 31.2.13 Current consumption in Reset and Reset Pulswidth 31.3 Atmel ATmega329A 31.3.1 Active supply current 31.3.2 Idle supply current 31.3.3 Atmel ATmega329A: Supply current of I/O modules 31.3.3.1 Example 1 31.3.4 Power-down supply current 31.3.5 Power-save supply current 31.3.6 Standby supply current 31.3.7 Pin pull-up 31.3.8 Pin driver strength 31.3.9 Pin Threshold and Hysteresis 31.3.10 BOD Thresholds and Analog Comparator offset 31.3.11 Internal oscillator speed 31.3.12 Current consumption of peripheral units 31.3.13 Current consumption in Reset and Reset Pulswidth 31.4 Atmel ATmega329PA 31.4.1 Active supply current 31.4.2 Idle supply current 31.4.3 Atmel ATmega329PA: Supply current of I/O modules 31.4.3.1 Example 1 31.4.4 Power-down supply current 31.4.5 Power-save supply current 31.4.6 Standby supply current 31.4.7 Pin pull-up 31.4.8 Pin driver strength 31.4.9 Pin Threshold and Hysteresis 31.4.10 BOD Thresholds and Analog Comparator offset 31.4.11 Internal oscillator speed 31.4.12 Current consumption of peripheral units 31.4.13 Current consumption in Reset and Reset Pulswidth 31.5 Atmel ATmega3290A 31.5.1 Active supply current 31.5.2 Idle supply current 31.5.3 Atmel ATmega3290A: Supply current of I/O modules 31.5.3.1 Example 1 31.5.4 Power-down supply current 31.5.5 Power-save supply current 31.5.6 Standby supply current 31.5.7 Pin pull-up 31.5.8 Pin driver strength 31.5.9 Pin Threshold and Hysteresis 31.5.10 BOD Thresholds and Analog Comparator offset 31.5.11 Internal oscillator speed 31.5.12 Current consumption of peripheral units 31.5.13 Current consumption in Reset and Reset Pulswidth 31.6 Atmel ATmega3290PA 31.6.1 Active supply current 31.6.2 Idle supply current 31.6.3 Atmel ATmega3290PA: Supply current of I/O modules 31.6.3.1 Example 1 31.6.4 Power-down supply current 31.6.5 Power-save supply current 31.6.6 Standby supply current 31.6.7 Pin pull-up 31.6.8 Pin driver strength 31.6.9 Pin Threshold and Hysteresis 31.6.10 BOD Thresholds and Analog Comparator offset 31.6.11 Internal oscillator speed 31.6.12 Current consumption of peripheral units 31.6.13 Current consumption in Reset and Reset Pulswidth 31.7 Atmel ATmega649A 31.7.1 Active supply current 31.7.2 Idle supply current 31.7.3 Atmel ATmega649A: Supply current of I/O modules 31.7.3.1 Example 1 31.7.4 Power-down supply current 31.7.5 Power-save supply current 31.7.6 Standby supply current 31.7.7 Pin pull-up 31.7.8 Pin driver strength 31.7.9 Pin Threshold and Hysteresis 31.7.10 BOD Thresholds and Analog Comparator offset 31.7.11 Internal oscillator speed 31.7.12 Current consumption of peripheral units 31.7.13 Current consumption in Reset and Reset Pulswidth 31.8 Atmel ATmega649P 31.8.1 Active supply current 31.8.2 Idle supply current 31.8.3 Atmel ATmega649P: Supply current of I/O modules 31.8.3.1 Example 1 31.8.4 Power-down supply current 31.8.5 Power-save supply current 31.8.6 Standby supply current 31.8.7 Pin pull-up 31.8.8 Pin driver strength 31.8.9 Pin Threshold and Hysteresis 31.8.10 BOD Thresholds and Analog Comparator offset 31.8.11 Internal oscillator speed 31.8.12 Current consumption of peripheral units 31.8.13 Current consumption in Reset and Reset Pulswidth 31.9 Atmel ATmega6490A 31.9.1 Active supply current 31.9.2 Idle supply current 31.9.3 Atmel ATmega6490A: Supply current of I/O modules 31.9.3.1 Example 1 31.9.4 Power-down supply current 31.9.5 Power-save supply current 31.9.6 Standby supply current 31.9.7 Pin pull-up 31.9.8 Pin driver strength 31.9.9 Pin Threshold and Hysteresis 31.9.10 BOD Thresholds and Analog Comparator offset 31.9.11 Internal oscillator speed 31.9.12 Current consumption of peripheral units 31.9.13 Current consumption in Reset and Reset Pulswidth 31.10 Atmel ATmega6490P 31.10.1 Active supply current 31.10.2 Idle supply current 31.10.3 Atmel ATmega6490P: Supply current of I/O modules 31.10.3.1 Example 1 31.10.4 Power-down supply current 31.10.5 Power-save supply current 31.10.6 Standby supply current 31.10.7 Pin pull-up 31.10.8 Pin driver strength 31.10.9 Pin Threshold and Hysteresis 31.10.10 BOD Thresholds and Analog Comparator offset 31.10.11 Internal oscillator speed 31.10.12 Current consumption of peripheral units 31.10.13 Current consumption in Reset and Reset Pulswidth 32. Typical Characteristics – TA = -40°C to 105°C 32.1 Typical characteristics ATmega169PA 32.1.1 Active Supply Current 32.1.2 Idle Supply Current 32.1.3 Power-down Supply Current 32.1.4 Power-save Supply Current 32.1.5 Standby Supply Current 32.1.6 Pin Pull-up 32.1.7 Pin Driver Strength 32.1.8 Pin Thresholds and Hysteresis 32.1.9 BOD Thresholds and Analog Comparator Offset 32.1.10 Internal Oscillator Speed 32.1.11 Current Consumption of Peripheral Units 32.1.12 Current Consumption in Reset and Reset Pulsewidth 32.2 ATmega329A 32.2.1 Active Supply Current 32.2.2 Idle Supply Current 32.2.3 Power-down Supply Current 32.2.4 Power-save Supply Current 32.2.5 Standby Supply Current 32.2.6 Pin Pull-up 32.2.7 Pin Driver Strength 32.2.8 Pin Thresholds and Hysteresis 32.2.9 BOD Thresholds and Analog Comparator Offset 32.2.10 Internal Oscillator Speed 32.2.11 Current Consumption of Peripheral Units 32.2.12 Current Consumption in Reset and Reset Pulsewidth 32.3 Typical characteristics ATmega329P 32.3.1 Active Supply Current 32.3.2 Idle Supply Current 32.3.3 Power-down Supply Current 32.3.4 Power-save Supply Current 32.3.5 Standby Supply Current 32.3.6 Pin Pull-up 32.3.7 Pin Driver Strength 32.3.8 Pin Thresholds and Hysteresis 32.3.9 BOD Thresholds and Analog Comparator Offset 32.3.10 Internal Oscillator Speed 32.3.11 Current Consumption of Peripheral Units 32.3.12 Current Consumption in Reset and Reset Pulsewidth 32.4 ATmega329PA - 105°C 32.4.1 Active Supply Current 32.4.2 Idle Supply Current 32.4.3 Power-down Supply Current 32.4.4 Power-save Supply Current 32.4.5 Standby Supply Current 32.4.6 Pin Pull-up 32.4.7 Pin Driver Strength 32.4.8 Pin Thresholds and Hysteresis 32.4.9 BOD Thresholds and Analog Comparator Offset 32.4.10 Internal Oscillator Speed 32.4.11 Current Consumption of Peripheral Units 32.4.12 Current Consumption in Reset and Reset Pulsewidth 32.5 ATmega3290A 32.5.1 Active Supply Current 32.5.2 Idle Supply Current 32.5.3 Power-down Supply Current 32.5.4 Power-save Supply Current 32.5.5 Standby Supply Current 32.5.6 Pin Pull-up 32.5.7 Pin Driver Strength 32.5.8 Pin Thresholds and Hysteresis 32.5.9 BOD Thresholds and Analog Comparator Offset 32.5.10 Internal Oscillator Speed 32.5.11 Current Consumption of Peripheral Units 32.5.12 Current Consumption in Reset and Reset Pulsewidth 32.6 Typical characteristics ATmega3290PA 32.6.1 Active Supply Current 32.6.2 Idle Supply Current 32.6.3 Power-down Supply Current 32.6.4 Power-save Supply Current 32.6.5 Standby Supply Current 32.6.6 Pin Pull-up 32.6.7 Pin Driver Strength 32.6.8 Pin Thresholds and Hysteresis 32.6.9 BOD Thresholds and Analog Comparator Offset 32.6.10 Internal Oscillator Speed 32.6.11 Current Consumption of Peripheral Units 32.6.12 Current Consumption in Reset and Reset Pulsewidth 32.7 ATmega3290PA - 105°C 32.7.1 Active Supply Current 32.7.2 Idle Supply Current 32.7.3 Power-down Supply Current 32.7.4 Power-save Supply Current 32.7.5 Standby Supply Current 32.7.6 Pin Pull-up 32.7.7 Pin Driver Strength 32.7.8 Pin Thresholds and Hysteresis 32.7.9 BOD Thresholds and Analog Comparator Offset 32.7.10 Internal Oscillator Speed 32.7.11 Current Consumption of Peripheral Units 32.7.12 Current Consumption in Reset and Reset Pulsewidth 33. Register summary 34. Instruction set summary 35. Ordering information 35.1 Atmel ATmega169A 35.2 Atmel ATmega169PA 35.3 Atmel ATmega329A 35.4 Atmel ATmega329PA 35.5 Atmel ATmega3290A 35.6 Atmel ATmega3290PA 35.7 Atmel ATmega649A 35.8 Atmel ATmega649P 35.9 Atmel ATmega6490A 35.10 Atmel ATmega6490P 36. Packaging Information 36.1 64A 36.2 64M1 36.3 64MC 36.4 100A 37. Errata 37.1 Atmel ATmega169A 37.2 Atmel ATmega169A/169PA Rev. A to F 37.3 Atmel ATmega169PA Rev. G 37.4 Atmel ATmega329A/329PA rev. A 37.5 Atmel ATmega329A/329PA rev. B 37.6 Atmel ATmega329A/329PA rev. C 37.7 Atmel ATmega3290A/3290PA rev. A 37.8 Atmel ATmega3290A/3290PA rev. B 37.9 Atmel ATmega3290A/3290PA rev. C 37.10 Atmel ATmega649A/649P/ATmega6490A/6490P 38. Datasheet revision history 38.1 Rev. 8284F - 08/2014 38.2 Rev. 8284E - 02/2013 38.3 Rev. 8284D - 06/11 38.4 Rev. 8284C - 06/11 38.5 Rev. 8284B - 03/11 38.6 Rev. 8284A - 10/10 Table of Content