Datasheet ATmega64A - Summary (Microchip) - 10
| Fabricante | Microchip |
| Descripción | 8-bit AVR Micrcontroller |
| Páginas / Página | 20 / 10 — 6.1.2. GND. 6.1.3. Port A (PA7:PA0). 6.1.4. Port B (PB7:PB0). 6.1.5. Port … |
| Formato / tamaño de archivo | PDF / 333 Kb |
| Idioma del documento | Inglés |
6.1.2. GND. 6.1.3. Port A (PA7:PA0). 6.1.4. Port B (PB7:PB0). 6.1.5. Port C (PC7:PC0). Note: . 6.1.6. Port D (PD7:PD0). 6.1.7. Port E (PE7:PE0)
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6.1.2. GND
Ground.
6.1.3. Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tristated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega64A as listed in Alternate Functions of Port A.
6.1.4. Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega64A as listed in Alternate Functions of Port B.
6.1.5. Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega64A as listed in Alternate Functions of Port C. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active.
Note:
The Atmel AVR ATmega64A is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled.
6.1.6. Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega64A as listed in Alternate Functions of Port D.
6.1.7. Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tristated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega64A as listed in Alternate Functions of Port E.
6.1.8. Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter. Atmel ATmega64A [DATASHEET] 10 Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. ATmega103 and ATmega64A Compatibility 5.1. ATmega103 Compatibility Mode 6. Pin Configurations 6.1. Pin Descriptions 6.1.1. VCC 6.1.2. GND 6.1.3. Port A (PA7:PA0) 6.1.4. Port B (PB7:PB0) 6.1.5. Port C (PC7:PC0) 6.1.6. Port D (PD7:PD0) 6.1.7. Port E (PE7:PE0) 6.1.8. Port F (PF7:PF0) 6.1.9. Port G (PG4:PG0) 6.1.10. RESET 6.1.11. XTAL1 6.1.12. XTAL2 6.1.13. AVCC 6.1.14. AREF 6.1.15. PEN 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 11. Packaging Information 11.1. 64A 11.2. 64M1 12. Errata 12.1. ATmega64A Rev. D
Ground.
6.1.3. Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tristated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega64A as listed in Alternate Functions of Port A.
6.1.4. Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega64A as listed in Alternate Functions of Port B.
6.1.5. Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega64A as listed in Alternate Functions of Port C. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active.
Note:
The Atmel AVR ATmega64A is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled.
6.1.6. Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega64A as listed in Alternate Functions of Port D.
6.1.7. Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tristated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega64A as listed in Alternate Functions of Port E.
6.1.8. Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter. Atmel ATmega64A [DATASHEET] 10 Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. ATmega103 and ATmega64A Compatibility 5.1. ATmega103 Compatibility Mode 6. Pin Configurations 6.1. Pin Descriptions 6.1.1. VCC 6.1.2. GND 6.1.3. Port A (PA7:PA0) 6.1.4. Port B (PB7:PB0) 6.1.5. Port C (PC7:PC0) 6.1.6. Port D (PD7:PD0) 6.1.7. Port E (PE7:PE0) 6.1.8. Port F (PF7:PF0) 6.1.9. Port G (PG4:PG0) 6.1.10. RESET 6.1.11. XTAL1 6.1.12. XTAL2 6.1.13. AVCC 6.1.14. AREF 6.1.15. PEN 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 11. Packaging Information 11.1. 64A 11.2. 64M1 12. Errata 12.1. ATmega64A Rev. D