Datasheet PIC16F1704, PIC16F1708, PIC16LF1704, PIC16LF1708 (Microchip) - 7

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PIC16(L)F1704/8 Table of Contents
Device Overview ... 9 Enhanced Mid-Range CPU ... 17 Memory Organization.. 19 Device Configuration ... 48 Resets ... 54 Oscillator Module (with Fail-Safe Clock Monitor) .. 62 Interrupts ... 80 Power-Down Mode (Sleep) ... 93 Watchdog Timer (WDT) .. 97 Flash Program Memory Control .. 102 I/O Ports .. 118 Peripheral Pin Select (PPS) Module ... 136 Interrupt-On-Change ... 143 Fixed Voltage Reference (FVR) ... 149 Temperature Indicator Module .. 152 Comparator Module .. 154 Pulse Width Modulation (PWM) .. 163 Complementary Output Generator (COG) Module ... 169 Configurable Logic Cell (CLC) .. 201 Analog-to-Digital Converter (ADC) Module ... 217 Operational Amplifier (OPA) Modules ... 231 8-Bit Digital-to-Analog Converter (DAC1) Module ... 234 Zero-Cross Detection (ZCD) Module .. 238 Timer0 Module .. 242 Timer1 Module with Gate Control ... 245 Timer2/4/6 Module .. 256 Capture/Compare/PWM Modules ... 261 Master Synchronous Serial Port (MSSP) Module .. 268 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .. 324 In-Circuit Serial Programming™ (ICSP™) .. 355 Instruction Set Summary ... 357 Electrical Specifications .. 371 DC and AC Characteristics Graphs and Charts .. 403 Development Support ... 425 Packaging Information .. 429 Appendix A: Data Sheet Revision History... 448 The Microchip Web Site .. 449 Customer Change Notification Service ... 449 Customer Support ... 449 Product Identification System ... 450  2013-2015 Microchip Technology Inc. DS40001715D-page 7 Document Outline High-Performance RISC CPU Flexible Oscillator Structure eXtreme Low-Power (XLP) Features Special Microcontroller Features Digital Peripheral Features Digital Peripheral Features (Continued) Analog Peripheral Features Pin Diagrams Pin Allocation Tables Table of Contents Most Current Data Sheet Errata Customer Notification System 14/20-Pin 8-Bit Advanced Analog Flash Microcontrollers 1.0 Device Overview TABLE 1-1: Device Peripheral Summary FIGURE 1-1: PIC16(L)F1704/8 Block Diagram TABLE 1-2: PIC16(L)F1704 PinOut Description TABLE 1-3: PIC16(L)F1708 Pin Out Description 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization TABLE 3-1: Device Sizes and Addresses FIGURE 3-1: Program Memory Map and Stack for PIC16(L)F1704/8 3.1.1 Reading Program Memory as Data EXAMPLE 3-1: RETLW Instruction EXAMPLE 3-2: Accessing Program Memory Via FSR 3.2 High-Endurance Flash 3.3 Data Memory Organization 3.3.1 Core Registers TABLE 3-2: Core Registers 3.4 Register Definitions: Status Register 3-1: STATUS: STATUS Register 3.4.1 Special Function Register 3.4.2 General Purpose RAM 3.4.3 Common RAM FIGURE 3-2: Banked Memory Partitioning 3.4.4 Device Memory Maps TABLE 3-3: PIC16(L)F1704 Memory Map (Banks 0-7) TABLE 3-4: PIC16(L)1708 Memory Map (Banks 0-7) TABLE 3-5: PIC16(L)F1704/8 Memory Map, Bank 8-23 TABLE 3-6: PIC16(L)F1704/8 Memory Map, Bank 24-31 TABLE 3-7: PIC16(L)F1704/8 Memory Map, Bank 28-30 TABLE 3-8: PIC16(L)F1704/8 Memory Map, Bank 31 3.4.5 Core Function Registers Summary TABLE 3-9: Core Function Registers Summary TABLE 3-10: Special Function Register Summary 3.5 PCL and PCLATH FIGURE 3-3: Loading of PC in Different Situations 3.5.1 Modifying PCL 3.5.2 Computed GOTO 3.5.3 Computed Function Calls 3.5.4 Branching 3.6 Stack 3.6.1 Accessing the Stack FIGURE 3-4: Accessing the Stack Example 1 FIGURE 3-5: Accessing the Stack Example 2 FIGURE 3-6: Accessing the Stack Example 3 FIGURE 3-7: Accessing the Stack Example 4 3.6.2 Overflow/Underflow Reset 3.7 Indirect Addressing FIGURE 3-8: Indirect Addressing 3.7.1 Traditional Data Memory FIGURE 3-9: Traditional Data Memory Map 3.7.2 Linear Data Memory FIGURE 3-10: Linear Data Memory Map 3.7.3 Program Flash Memory FIGURE 3-11: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words 4.2 Register Definitions: Configuration Words Register 4-1: CONFIG1: Configuration Word 1 Register 4-2: CONFIG2: Configuration Word 2 4.3 Code Protection 4.3.1 Program Memory Protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device and Revision Register 4-3: DevID: Device ID Register Register 4-4: RevID: Revision ID Register 5.0 Resets FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit 5.1 Power-On Reset (POR) 5.1.1 Power-up Timer (PWRT) 5.2 Brown-Out Reset (BOR) TABLE 5-1: BOR Operating Modes 5.2.1 BOR is Always On 5.2.2 BOR is Off in Sleep 5.2.3 BOR Controlled by Software FIGURE 5-2: Brown-Out Situations 5.3 Register Definitions: BOR Control Register 5-1: BORCON: Brown-Out Reset Control Register 5.4 Low-Power Brown-Out Reset (LPBOR) 5.4.1 Enabling LPBOR 5.5 MCLR TABLE 5-2: MCLR Configuration 5.5.1 MCLR Enabled 5.5.2 MCLR Disabled 5.6 Watchdog Timer (WDT) Reset 5.7 RESET Instruction 5.8 Stack Overflow/Underflow Reset 5.9 Programming Mode Exit 5.10 Power-Up Timer 5.11 Start-up Sequence FIGURE 5-3: Reset Start-up Sequence 5.12 Determining the Cause of a Reset TABLE 5-3: Reset Status Bits and Their Significance TABLE 5-4: Reset Condition for Special Registers 5.13 Power Control (PCON) Register 5.14 Register Definitions: Power Control Register 5-2: PCON: Power Control Register TABLE 5-5: Summary of Registers Associated with Resets 6.0 Oscillator Module (with Fail-Safe Clock Monitor) 6.1 Overview FIGURE 6-1: Simplified PIC® MCU Clock Source Block Diagram 6.2 Clock Source Types 6.2.1 External Clock Sources FIGURE 6-2: External Clock (EC) Mode Operation FIGURE 6-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 6-4: Ceramic Resonator Operation (XT or HS Mode) FIGURE 6-5: Quartz Crystal Operation (Secondary Oscillator) FIGURE 6-6: External RC Modes 6.2.2 Internal Clock Sources FIGURE 6-7: Internal Oscillator Switch Timing 6.3 Clock Switching 6.3.1 System Clock Select (SCS) Bits 6.3.2 Oscillator Start-up Timer Status (OSTS) Bit 6.3.3 Secondary Oscillator 6.3.4 Secondary Oscillator Ready (SOSCR) Bit 6.3.5 Clock Switching Before Sleep 6.4 Two-Speed Clock Start-up Mode 6.4.1 Two-Speed Start-up Mode Configuration TABLE 6-1: Oscillator Switching Delays 6.4.2 Two-speed Start-up Sequence 6.4.3 Checking Two-Speed Clock Status FIGURE 6-8: Two-Speed Start-up 6.5 Fail-Safe Clock Monitor FIGURE 6-9: FSCM Block Diagram 6.5.1 Fail-Safe Detection 6.5.2 Fail-Safe Operation 6.5.3 Fail-Safe Condition Clearing 6.5.4 Reset or Wake-up from Sleep FIGURE 6-10: FSCM Timing Diagram 6.6 Register Definitions: Oscillator Control Register 6-1: OSCCON: Oscillator Control Register Register 6-2: OSCSTAT: Oscillator Status Register Register 6-3: OSCTUNE: Oscillator Tuning Register TABLE 6-2: Summary of Registers Associated with Clock Sources TABLE 6-3: Summary of Configuration Word with Clock Sources 7.0 Interrupts FIGURE 7-1: Interrupt Logic 7.1 Operation 7.2 Interrupt Latency FIGURE 7-2: Interrupt Latency FIGURE 7-3: INT Pin Interrupt Timing 7.3 Interrupts During Sleep 7.4 INT Pin 7.5 Automatic Context Saving 7.6 Register Definitions: Interrupt Control Register 7-1: INTCON: Interrupt Control Register Register 7-2: PIE1: Peripheral Interrupt Enable Register 1 Register 7-3: PIE2: Peripheral Interrupt Enable Register 2 Register 7-4: PIE3: Peripheral Interrupt Enable Register 3 Register 7-5: PIR1: Peripheral Interrupt Request Register 1 Register 7-6: PIR2: Peripheral Interrupt Request Register 2 Register 7-7: PIR3: Peripheral Interrupt Request Register 3 TABLE 7-1: Summary of Registers Associated with Interrupts 8.0 Power-Down Mode (Sleep) 8.1 Wake-up from Sleep 8.1.1 Wake-up Using Interrupts FIGURE 8-1: Wake-Up From Sleep Through Interrupt 8.2 Low-Power Sleep Mode 8.2.1 Sleep Current vs. Wake-up Time 8.2.2 Peripheral Usage in Sleep 8.3 Register Definitions: Voltage Regulator Control Register 8-1: VREGCON: Voltage Regulator Control Register(1) TABLE 8-1: Summary of Registers Associated with Power-Down Mode 9.0 Watchdog Timer (WDT) FIGURE 9-1: Watchdog Timer Block Diagram 9.1 Independent Clock Source 9.2 WDT Operating Modes 9.2.1 WDT is Always On 9.2.2 WDT is Off in Sleep 9.2.3 WDT Controlled By Software TABLE 9-1: WDT Operating Modes 9.3 Time-Out Period 9.4 Clearing the WDT 9.5 Operation During Sleep TABLE 9-2: WDT Clearing Conditions 9.6 Register Definitions: Watchdog Control Register 9-1: WDTCON: Watchdog Timer Control Register TABLE 9-3: Summary of Registers Associated with Watchdog Timer TABLE 9-4: Summary of Configuration Word with Watchdog Timer 10.0 Flash Program Memory Control 10.1 PMADRL and PMADRH Registers 10.1.1 PMCON1 and PMCON2 Registers 10.2 Flash Program Memory Overview TABLE 10-1: Flash Memory Organization By Device 10.2.1 Reading the Flash Program Memory FIGURE 10-1: Flash Program Memory Read Flowchart FIGURE 10-2: Flash Program Memory Read Cycle Execution EXAMPLE 10-1: Flash Program Memory Read 10.2.2 Flash Memory Unlock Sequence FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart 10.2.3 Erasing Flash Program Memory FIGURE 10-4: Flash Program Memory Erase Flowchart EXAMPLE 10-2: Erasing One Row of Program Memory 10.2.4 Writing to Flash Program Memory FIGURE 10-5: Block Writes to Flash Program Memory With 32 write latches FIGURE 10-6: Flash Program Memory Write Flowchart EXAMPLE 10-3: Writing to Flash Program Memory 10.3 Modifying Flash Program Memory FIGURE 10-7: Flash Program Memory Modify Flowchart 10.4 User ID, Device ID and Configuration Word Access TABLE 10-2: User ID, Device ID and Configuration Word Access (CFGS = 1) EXAMPLE 10-4: Configuration Word and Device ID Access 10.5 Write Verify FIGURE 10-8: Flash Program Memory Verify Flowchart 10.6 Register Definitions: Flash Program Memory Control Register 10-1: PMDATL: Program Memory Data Low Byte Register Register 10-2: PMDATH: Program Memory Data High Byte Register Register 10-3: PMADRL: Program Memory Address Low Byte Register Register 10-4: PMADRH: Program Memory Address High Byte Register Register 10-5: PMCON1: Program Memory Control 1 Register Register 10-6: PMCON2: Program Memory Control 2 Register TABLE 10-3: Summary of Registers Associated with Flash Program Memory TABLE 10-4: Summary of Configuration Word with Flash Program Memory 11.0 I/O Ports TABLE 11-1: Port Availability Per Device FIGURE 11-1: Generic I/O Port Operation 11.1 PORTA Registers 11.1.1 Data Register 11.1.2 Direction Control 11.1.3 Open-Drain Control 11.1.4 Slew Rate Control 11.1.5 Input Threshold Control 11.1.6 Analog Control EXAMPLE 11-1: Initializing PORTA 11.1.7 PORTA Functions and Output Priorities 11.2 Register Definitions: PORTA Register 11-1: PORTA: PORTA Register Register 11-2: TRISA: PORTA Tri-State Register Register 11-3: LATA: PORTA Data Latch Register Register 11-4: ANSELA: PORTA Analog Select Register Register 11-5: WPUA: Weak Pull-Up PORTA Register Register 11-6: ODCONA: PORTA Open-Drain Control Register Register 11-7: SLRCONA: PORTA Slew Rate Control Register Register 11-8: INLVLA: PORTA Input Level Control Register TABLE 11-2: Summary of Registers Associated with PORTA TABLE 11-3: Summary of Configuration Word with PORTA 11.3 PORTB Registers (PIC16(L)F1708 only) 11.3.1 Direction Control 11.3.2 Open-Drain Control 11.3.3 Slew Rate Control 11.3.4 Input Threshold Control 11.3.5 Analog Control 11.3.6 PORTB Functions and Output Priorities 11.4 Register Definitions: PORTB Register 11-9: PORTB: PORTB Register Register 11-10: TRISB: PORTB Tri-State Register Register 11-11: LATB: PORTB Data Latch Register Register 11-12: ANSELB: PORTB Analog Select Register Register 11-13: WPUB: Weak Pull-Up PORTB Register Register 11-14: ODCONB: PORTB Open-Drain Control Register Register 11-15: SLRCONB: PORTB Slew Rate Control Register Register 11-16: INLVLB: PORTB Input Level Control Register TABLE 11-4: Summary of Registers Associated with PORTB 11.5 PORTC Registers 11.5.1 Data Register 11.5.2 Direction Control 11.5.3 Input Threshold Control 11.5.4 Open-Drain Control 11.5.5 Slew Rate Control 11.5.6 Analog Control 11.5.7 PORTC Functions and Output Priorities 11.6 Register Definitions: PORTC Register 11-17: PORTC: PORTC Register Register 11-18: TRISC: PORTC Tri-State Register Register 11-19: LATC: PORTC Data Latch Register Register 11-20: ANSELC: PORTC Analog Select Register Register 11-21: WPUC: Weak Pull-Up PORTC Register Register 11-22: ODCONC: PORTC Open-Drain Control Register Register 11-23: SLRCONC: PORTC Slew Rate Control Register Register 11-24: INLVLC: PORTC Input Level Control Register TABLE 11-5: Summary of Registers Associated with PORTC 12.0 Peripheral Pin Select (PPS) Module 12.1 PPS Inputs 12.2 PPS Outputs FIGURE 12-1: Simplified PPS Block Diagram 12.3 Bidirectional Pins 12.4 PPS Lock EXAMPLE 12-1: PPS Lock/Unlock sequence 12.5 PPS Permanent Lock 12.6 Operation During Sleep 12.7 Effects of a Reset 12.8 Register Definitions: PPS Input Selection Register 12-1: xxxPPS: Peripheral xxx input Selection (PIC16(L)F1704) Register 12-2: xxxPPS: Peripheral xxx input Selection (PIC16(L)F1708) Register 12-3: RxyPPS: Pin Rxy Output Source Selection Register Register 12-4: PPSLOCK: PPS Lock Register TABLE 12-1: Summary of Registers Associated with the PPS Module 13.0 Interrupt-On-Change 13.1 Enabling the Module 13.2 Individual Pin Configuration 13.3 Interrupt Flags 13.4 Clearing Interrupt Flags EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example) 13.5 Operation in Sleep FIGURE 13-1: Interrupt-On-Change Block Diagram (PORTA Example) 13.6 Register Definitions: Interrupt-on-Change Control Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 13-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register(1) Register 13-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register(1) Register 13-6: IOCBF: Interrupt-on-Change PORTB Flag Register(1) Register 13-7: IOCCP: Interrupt-on-Change PORTC Positive Edge Register Register 13-8: IOCCN: Interrupt-on-Change PORTC Negative Edge Register Register 13-9: IOCCF: Interrupt-on-Change PORTC Flag Register TABLE 13-1: Summary of Registers Associated with Interrupt-On-Change 14.0 Fixed Voltage Reference (FVR) 14.1 Independent Gain Amplifiers 14.2 FVR Stabilization Period FIGURE 14-1: Voltage Reference Block Diagram TABLE 14-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 14.3 FVR Buffer Stabilization Period 14.4 Register Definitions: FVR Control Register 14-1: FVRCON: Fixed Voltage Reference Control Register TABLE 14-2: Summary of Registers Associated with Fixed Voltage Reference 15.0 Temperature Indicator Module 15.1 Circuit Operation EQUATION 15-1: Vout Ranges FIGURE 15-1: Temperature Circuit Diagram 15.2 Minimum Operating Vdd TABLE 15-1: Recommended Vdd vs. Range 15.3 Temperature Output 15.4 ADC Acquisition Time TABLE 15-2: Summary of Registers Associated with the Temperature Indicator 16.0 Comparator Module 16.1 Comparator Overview TABLE 16-1: Available Comparators FIGURE 16-1: Single Comparator FIGURE 16-2: Comparator Module Simplified Block Diagram 16.2 Comparator Control 16.2.1 Comparator Enable 16.2.2 Comparator Output Selection 16.2.3 Comparator Output Polarity TABLE 16-2: Comparator Output State vs. Input Conditions 16.2.4 Comparator Speed/Power Selection 16.3 Comparator Hysteresis 16.4 Timer1 Gate Operation 16.4.1 Comparator Output Synchronization 16.5 Comparator Interrupt 16.6 Comparator Positive Input Selection 16.7 Comparator Negative Input Selection 16.8 Comparator Response Time 16.9 Zero Latency Filter FIGURE 16-3: Comparator Zero Latency Filter Operation 16.10 Analog Input Connection Considerations FIGURE 16-4: Analog Input Model 16.11 Register Definitions: Comparator Control Register 16-1: CMxCON0: Comparator Cx Control Register 0 Register 16-2: CMxCON1: Comparator Cx Control Register 1 Register 16-3: CMOUT: Comparator Output Register TABLE 16-3: Summary of Registers Associated with Comparator Module 17.0 Pulse Width Modulation (PWM) FIGURE 17-1: Simplified PWM Block Diagram FIGURE 17-2: PWM Output 17.1 PWMx Pin Configuration 17.1.1 Fundamental Operation 17.1.2 PWM Output Polarity 17.1.3 PWM Period EQUATION 17-1: PWM Period 17.1.4 PWM Duty Cycle EQUATION 17-2: Pulse Width EQUATION 17-3: Duty Cycle Ratio 17.1.5 PWM Resolution EQUATION 17-4: PWM Resolution TABLE 17-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 17-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 17.1.6 Operation in Sleep Mode 17.1.7 Changes in System Clock Frequency 17.1.8 Effects of Reset 17.1.9 Setup for PWM Operation using PWMx Pins 17.1.10 Setup for PWM Operation to Other Device Peripherals 17.2 Register Definitions: PWM Control Register 17-1: PWMxCON: PWM Control Register Register 17-2: PWMXDCH: PWM Duty Cycle High Bits Register 17-3: PWMxDCL: PWM Duty Cycle Low Bits TABLE 17-3: Summary of Registers Associated with PWM 18.0 Complementary Output Generator (COG) Module 18.1 Fundamental Operation 18.1.1 Steering (all modes) 18.1.2 Steered PWM Modes 18.1.3 Full-Bridge Modes FIGURE 18-1: Example of Full-Bridge Application 18.1.4 Half-Bridge Mode 18.1.5 Push-Pull Mode 18.1.6 Event driven PWM (all modes) FIGURE 18-2: Simplified COG Block Diagram (Steered PWM Mode, GxMD = 0) FIGURE 18-3: Simplified COG Block Diagram (Synchronous Steered PWM Mode, GxMD = 1) FIGURE 18-4: Simplified COG Block Diagram (Full-Bridge Modes, Forward: GxMD = 2, Reverse: GxMD = 3) FIGURE 18-5: Simplified COG Block Diagram (Half-Bridge Mode, GxMD = 4) FIGURE 18-6: Simplified COG Block Diagram (Push-Pull Mode, GxMD = 5) FIGURE 18-7: COG (Rising/Falling) Input Block FIGURE 18-8: COG (Rising/Falling) Dead-band block FIGURE 18-9: Typical Half-Bridge mode COG Operation with CCP1 FIGURE 18-10: Half-Bridge Mode COG operation with CCP1 and Phase Delay FIGURE 18-11: Push-Pull mode COG operation with CCP1 FIGURE 18-12: Full-Bridge Forward mode COG operation with CCP1 FIGURE 18-13: Full-Bridge Mode COG Operation with CCP1 and Direction Change 18.2 Clock Sources 18.3 Selectable Event Sources 18.3.1 Edge vs. Level Sensing FIGURE 18-14: Edge Vs Level Sense 18.3.2 Rising Event 18.3.3 Falling Event 18.4 Output Control 18.4.1 Output Enables TABLE 18-1: Pin Output States 18.4.2 Polarity Control 18.5 Dead-Band Control 18.5.1 Asynchronous delay chain dead-band delay 18.5.2 Synchronous counter dead-band delay 18.5.3 Synchronous counter Dead-band Time Uncertainty 18.5.4 Rising Event Dead-band 18.5.5 falling event Dead-band 18.5.6 Dead-band Overlap 18.6 Blanking Control 18.6.1 Falling event blanking of rising event Inputs 18.6.2 Rising event blanking of falling event Inputs 18.6.3 Blanking Time Uncertainty 18.7 Phase Delay 18.7.1 Cumulative Uncertainty EQUATION 18-1: Phase, Dead-Band, and Blanking Time Calculation EXAMPLE 18-1: Timer Uncertainty 18.8 Auto-shutdown Control 18.8.1 Shutdown 18.8.2 PIN Override Levels 18.8.3 Auto-Shutdown restart FIGURE 18-15: Auto-SHUTDOWN waveform – CCP1 as Rising and falling event Input Source 18.9 Buffer Updates 18.10 Input and Output Pin Selection 18.11 Operation During Sleep 18.12 Configuring the COG 18.13 Register Definitions: COG Control Register 18-1: COGxCON0: COG Control Register 0 Register 18-2: COGxCON1: COG Control Register 1 Register 18-3: COGxRIS: COG Rising Event Input Selection Register Register 18-4: COGxRSIM: COG Rising Event Source Input MOde Register Register 18-5: COGxFIS: COG Falling Event Input Selection Register Register 18-6: COGxFSIM: COG Falling Event Source Input Mode Register Register 18-7: COGXASD0: COG Auto-Shutdown Control Register 0 Register 18-8: COGXASD1: COG Auto-Shutdown Control Register 1 Register 18-9: COGXSTR: COG Steering Control Register 1 Register 18-10: COGXDBR: COG Rising Event Dead-Band Count Register Register 18-11: COGXDBF: COG Falling Event Dead-Band Count Register Register 18-12: COGXBLKR: COG Rising Event Blanking Count Register Register 18-13: COGXBLKF: COG Falling Event Blanking Count Register Register 18-14: COGXPHR: COG Rising Edge Phase Delay Count Register Register 18-15: COGXPHF: COG Falling Edge Phase Delay Count Register TABLE 18-2: Summary of Registers Associated with COG 19.0 Configurable Logic Cell (CLC) FIGURE 19-1: CLCx Simplified Block Diagram 19.1 CLCx Setup 19.1.1 Data Selection TABLE 19-1: CLCx Data Input Selection 19.1.2 Data Gating TABLE 19-2: Data Gating Logic 19.1.3 Logic Function 19.1.4 Output Polarity 19.1.5 CLCx Setup Steps 19.2 CLCx Interrupts 19.3 Output Mirror Copies 19.4 Effects of a Reset 19.5 Operation During Sleep FIGURE 19-2: Input Data Selection and Gating FIGURE 19-3: Programmable Logic Functions 19.6 Register Definitions: CLC Control Register 19-1: CLCxCON: Configurable Logic Cell Control Register Register 19-2: CLCxPOL: Signal Polarity Control Register Register 19-3: CLCxSEL0: Generic CLCx Data 1 Select Register Register 19-4: CLCxSEL1: Generic CLCx Data 2 Select Register Register 19-5: CLCxSEL2: Generic CLCx Data 3 Select Register Register 19-6: CLCxSEL3: Generic CLCx Data 4 Select Register Register 19-7: CLCxGLS0: Gate 1 Logic Select Register Register 19-8: CLCxGLS1: Gate 2 Logic Select Register Register 19-9: CLCxGLS2: Gate 3 Logic Select Register Register 19-10: CLCxGLS3: Gate 4 Logic Select Register Register 19-11: CLCDATA: CLC Data Output TABLE 19-3: Summary of Registers Associated with CLCx 20.0 Analog-to-Digital Converter (ADC) Module FIGURE 20-1: ADC Block Diagram 20.1 ADC Configuration 20.1.1 Port Configuration 20.1.2 Channel Selection 20.1.3 ADC Voltage Reference 20.1.4 Conversion Clock TABLE 20-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 20-2: Analog-to-Digital Conversion Tad Cycles 20.1.5 Interrupts 20.1.6 Result Formatting FIGURE 20-3: 10-Bit ADC Conversion Result Format 20.2 ADC Operation 20.2.1 Starting a Conversion 20.2.2 Completion of a Conversion 20.2.3 Terminating a Conversion 20.2.4 ADC Operation During Sleep 20.2.5 Auto-Conversion Trigger TABLE 20-2: Auto-Conversion Sources 20.2.6 ADC Conversion Procedure EXAMPLE 20-1: ADC Conversion 20.3 Register Definitions: ADC Control Register 20-1: ADCON0: ADC Control Register 0 Register 20-2: ADCON1: ADC Control Register 1 Register 20-3: ADCON2: ADC Control Register 2 Register 20-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 20-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 20-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 20-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 20.4 ADC Acquisition Requirements EQUATION 20-1: Acquisition Time Example FIGURE 20-4: Analog Input Model FIGURE 20-5: ADC Transfer Function TABLE 20-3: Summary of Registers Associated with ADC 21.0 Operational Amplifier (OPA) Modules FIGURE 21-1: OPAx Module Block Diagram 21.1 OPA Module Performance 21.1.1 OPA Module Control 21.1.2 Unity Gain Mode 21.2 Effects of Reset 21.3 Register Definitions: Op Amp Control Register 21-1: OPAxCON: Operational Amplifiers (OPAx) Control Registers TABLE 21-1: Summary of Registers Associated with Op Amps 22.0 8-Bit Digital-to-Analog Converter (DAC1) Module 22.1 Output Voltage Selection EQUATION 22-1: DAC Output Voltage 22.2 Ratiometric Output Level 22.3 DAC Voltage Reference Output FIGURE 22-1: Digital-to-Analog Converter Block Diagram FIGURE 22-2: Voltage Reference Output Buffer Example 22.4 Operation During Sleep 22.5 Effects of a Reset 22.6 Register Definitions: DAC Control Register 22-1: DAC1CON0: Voltage Reference Control Register 0 Register 22-2: DAC1CON1: Voltage Reference Control Register 1 TABLE 22-1: Summary of Registers Associated with the DAC1 Module 23.0 Zero-Cross Detection (ZCD) Module 23.1 External Resistor Selection EQUATION 23-1: External Resistor FIGURE 23-1: External Voltage FIGURE 23-2: Simplified ZCD Block Diagram 23.2 ZCD Logic Output 23.3 ZCD Logic Polarity 23.4 ZCD Interrupts 23.5 Correcting for Zcpinv offset EQUATION 23-2: ZCD Event Offset EQUATION 23-3: ZCD Pull-up/down EQUATION 23-4: 23.6 Handling Vpeak Variations EQUATION 23-5: Series R for V range 23.7 Operation During Sleep 23.8 Effects of a Reset 23.9 Register Definitions: ZCD Control Register 23-1: ZCDxCON: Zero-Cross Detection Control Register TABLE 23-1: Summary of Registers Associated with the ZCD Module TABLE 23-2: Summary of Configuration Word with the ZCD Module 24.0 Timer0 Module 24.1 Timer0 Operation 24.1.1 8-bit Timer Mode 24.1.2 8-bit Counter Mode FIGURE 24-1: Block Diagram of the Timer0 24.1.3 Software Programmable Prescaler 24.1.4 Timer0 Interrupt 24.1.5 8-bit Counter Mode Synchronization 24.1.6 Operation During Sleep 24.2 Register Definitions: Option Register Register 24-1: OPTION_REG: OPTION Register TABLE 24-1: Summary of Registers Associated with Timer0 25.0 Timer1 Module with Gate Control FIGURE 25-1: Timer1 Block Diagram 25.1 Timer1 Operation TABLE 25-1: Timer1 Enable Selections 25.2 Clock Source Selection 25.2.1 Internal Clock Source 25.2.2 External Clock Source TABLE 25-2: Clock Source Selections 25.3 Timer1 Prescaler 25.4 Timer1 (Secondary) Oscillator 25.5 Timer1 Operation in Asynchronous Counter Mode 25.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode 25.6 Timer1 Gate 25.6.1 Timer1 Gate Enable TABLE 25-3: Timer1 Gate Enable Selections 25.6.2 Timer1 Gate Source Selection TABLE 25-4: Timer1 Gate Sources 25.6.3 Timer1 Gate Toggle Mode 25.6.4 Timer1 Gate Single-Pulse Mode 25.6.5 Timer1 Gate Value Status 25.6.6 Timer1 Gate Event Interrupt 25.7 Timer1 Interrupt 25.8 Timer1 Operation During Sleep 25.9 CCP Capture/Compare Time Base 25.10 CCP Auto-Conversion Trigger FIGURE 25-2: Timer1 Incrementing Edge FIGURE 25-3: Timer1 Gate Enable Mode FIGURE 25-4: Timer1 Gate Toggle Mode FIGURE 25-5: Timer1 Gate Single-Pulse Mode FIGURE 25-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 25.11 Register Definitions: Timer1 Control Register 25-1: T1CON: Timer1 Control Register Register 25-2: T1GCON: Timer1 Gate Control Register TABLE 25-5: Summary of Registers Associated with Timer1 26.0 Timer2/4/6 Module FIGURE 26-1: Timer2 Block Diagram 26.1 Timer2 Operation 26.2 Timer2 Interrupt 26.3 Timer2 Output 26.4 Timer2 Operation During Sleep 26.5 Register Definitions: Timer2 Control Register 26-1: T2CON: Timer2 Control Register TABLE 26-1: Summary of Registers Associated with Timer2 26.6 CCP/PWM Clock Selection 26.7 Register Definitions: CCP/PWM Timers Control Register 26-2: CCPTMRS: PWM Timer Selection Control Register 0 27.0 Capture/Compare/PWM Modules 27.1 Capture Mode 27.1.1 CCP Pin Configuration FIGURE 27-1: Capture Mode Operation Block Diagram 27.1.2 Timer1 Mode Resource 27.1.3 Software Interrupt Mode 27.1.4 CCP Prescaler EXAMPLE 27-1: Changing Between Capture Prescalers 27.1.5 Capture During Sleep 27.2 Compare Mode FIGURE 27-2: Compare Mode Operation Block Diagram 27.2.1 CCPx Pin Configuration 27.2.2 Timer1 Mode Resource 27.2.3 Software Interrupt Mode 27.2.4 Auto-Conversion Trigger 27.2.5 Compare During Sleep 27.3 PWM Overview 27.3.1 Standard PWM Operation FIGURE 27-3: CCP PWM Output Signal FIGURE 27-4: Simplified PWM Block Diagram 27.3.2 Setup for PWM Operation 27.3.3 Timer2 Timer Resource 27.3.4 PWM Period EQUATION 27-1: PWM Period 27.3.5 PWM Duty Cycle EQUATION 27-2: Pulse Width EQUATION 27-3: Duty Cycle Ratio 27.3.6 PWM Resolution EQUATION 27-4: PWM Resolution TABLE 27-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 27-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 27.3.7 Operation in Sleep Mode 27.3.8 Changes in System Clock Frequency 27.3.9 Effects of Reset TABLE 27-3: Summary of Registers Associated with Standard PWM 27.4 Register Definitions: CCP Control Register 27-1: CCPXCON: CCPx Control Register 28.0 Master Synchronous Serial Port (MSSP) Module 28.1 MSSP Module Overview FIGURE 28-1: MSSP Block Diagram (SPI mode) FIGURE 28-2: MSSP Block Diagram (I2C Master mode) FIGURE 28-3: MSSP Block Diagram (I2C Slave mode) 28.2 SPI Mode Overview FIGURE 28-4: SPI Master and Multiple Slave Connection 28.2.1 SPI Mode Registers 28.2.2 SPI Mode Operation FIGURE 28-5: SPI Master/Slave Connection 28.2.3 SPI Master Mode FIGURE 28-6: SPI Mode Waveform (Master Mode) 28.2.4 SPI Slave Mode 28.2.5 Slave Select Synchronization FIGURE 28-7: SPI Daisy-Chain Connection FIGURE 28-8: Slave Select Synchronous Waveform FIGURE 28-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 28-10: SPI Mode Waveform (Slave Mode with CKE = 1) 28.2.6 SPI Operation in Sleep Mode TABLE 28-1: Summary of Registers Associated with SPI Operation 28.3 I2C Mode Overview FIGURE 28-11: I2C Master/ Slave Connection 28.3.1 Clock Stretching 28.3.2 Arbitration 28.4 I2C Mode Operation 28.4.1 Byte Format 28.4.2 Definition of I2C Terminology 28.4.3 SDA and SCL Pins 28.4.4 SDA Hold Time TABLE 28-2: I2C Bus terms 28.4.5 Start Condition 28.4.6 Stop Condition 28.4.7 Restart Condition 28.4.8 Start/Stop Condition Interrupt masking FIGURE 28-12: I2C Start and Stop Conditions FIGURE 28-13: I2C Restart Condition 28.4.9 Acknowledge Sequence 28.5 I2C Slave Mode Operation 28.5.1 Slave Mode Addresses 28.5.2 Slave Reception FIGURE 28-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 28-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 28-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 28-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) 28.5.3 Slave Transmission FIGURE 28-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) FIGURE 28-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) 28.5.4 Slave Mode 10-bit Address Reception 28.5.5 10-bit Addressing with Address or Data Hold FIGURE 28-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 28-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 28-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) 28.5.6 Clock Stretching 28.5.7 Clock Synchronization and the CKP bit FIGURE 28-23: Clock Synchronization Timing 28.5.8 General Call Address Support FIGURE 28-24: Slave Mode General Call Address Sequence 28.5.9 SSP Mask Register 28.6 I2C Master Mode 28.6.1 I2C Master Mode Operation 28.6.2 Clock Arbitration FIGURE 28-25: Baud Rate Generator Timing with Clock Arbitration 28.6.3 WCOL Status Flag 28.6.4 I2C Master Mode Start Condition Timing FIGURE 28-26: First Start Bit Timing 28.6.5 I2C Master Mode Repeated Start Condition Timing FIGURE 28-27: Repeated Start Condition Waveform 28.6.6 I2C Master Mode Transmission FIGURE 28-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) 28.6.7 I2C Master Mode Reception FIGURE 28-29: I2C Master Mode Waveform (Reception, 7-bit Address) 28.6.8 Acknowledge Sequence Timing 28.6.9 Stop Condition Timing FIGURE 28-30: Acknowledge Sequence Waveform FIGURE 28-31: Stop Condition Receive or Transmit Mode 28.6.10 Sleep Operation 28.6.11 Effects of a Reset 28.6.12 Multi-Master Mode 28.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration FIGURE 28-32: Bus Collision Timing for Transmit and Acknowledge FIGURE 28-33: Bus Collision During Start Condition (SDA Only) FIGURE 28-34: Bus Collision During Start Condition (SCL = 0) FIGURE 28-35: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 28-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 28-37: Bus Collision During Repeated Start Condition (Case 2) FIGURE 28-38: Bus Collision During a Stop Condition (Case 1) FIGURE 28-39: Bus Collision During a Stop Condition (Case 2) TABLE 28-3: Summary of Registers Associated with I2C Operation 28.7 Baud Rate Generator FIGURE 28-40: Baud Rate Generator Block Diagram TABLE 28-4: MSSP Clock Rate w/BRG 28.8 Register Definitions: MSSP Control Register 28-1: SSP1STAT: SSP STATUS Register Register 28-2: SSP1CON1: SSP Control Register 1 Register 28-3: SSP1CON2: SSP Control Register 2(1) Register 28-4: SSP1CON3: SSP Control Register 3 Register 28-5: SSP1MSK: SSP Mask Register Register 28-6: SSP1ADD: MSSP Address and Baud Rate Register (I2C Mode) 29.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 29-1: EUSART Transmit Block Diagram FIGURE 29-2: EUSART Receive Block Diagram 29.1 EUSART Asynchronous Mode 29.1.1 EUSART Asynchronous Transmitter FIGURE 29-3: Asynchronous Transmission FIGURE 29-4: Asynchronous Transmission (Back-to-Back) TABLE 29-1: Summary of Registers Associated with Asynchronous Transmission 29.1.2 EUSART Asynchronous Receiver FIGURE 29-5: Asynchronous Reception TABLE 29-2: Summary of Registers Associated with Asynchronous Reception 29.2 Clock Accuracy with Asynchronous Operation 29.3 Register Definitions: EUSART Control Register 29-1: TX1STA: Transmit Status and Control Register Register 29-2: RC1STA: Receive Status and Control Register Register 29-3: BAUD1CON: Baud Rate Control Register 29.4 EUSART Baud Rate Generator (BRG) EXAMPLE 29-1: Calculating Baud Rate Error TABLE 29-3: Baud Rate Formulas TABLE 29-4: Summary of Registers Associated with the Baud Rate Generator TABLE 29-5: BAUD Rates for Asynchronous Modes 29.4.1 Auto-Baud Detect TABLE 29-6: BRG Counter Clock Rates FIGURE 29-6: Automatic Baud Rate Calibration 29.4.2 Auto-Baud Overflow 29.4.3 Auto-Wake-up on Break FIGURE 29-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 29-8: Auto-Wake-up Bit (WUE) Timings During Sleep 29.4.4 Break Character Sequence 29.4.5 Receiving a Break Character FIGURE 29-9: Send Break Character Sequence 29.5 EUSART Synchronous Mode 29.5.1 Synchronous Master Mode FIGURE 29-10: Synchronous Transmission FIGURE 29-11: Synchronous Transmission (Through TXEN) TABLE 29-7: Summary of Registers Associated with Synchronous Master Transmission FIGURE 29-12: Synchronous Reception (Master Mode, SREN) TABLE 29-8: Summary of Registers Associated with Synchronous Master Reception 29.5.2 Synchronous slave Mode TABLE 29-9: Summary of Registers Associated with Synchronous Slave Transmission TABLE 29-10: Summary of Registers Associated with Synchronous Slave Reception 29.6 EUSART Operation During Sleep 29.6.1 Synchronous Receive During Sleep 29.6.2 Synchronous Transmit During Sleep 30.0 In-Circuit Serial Programming™ (ICSP™) 30.1 High-Voltage Programming Entry Mode 30.2 Low-Voltage Programming Entry Mode 30.3 Common Programming Interfaces FIGURE 30-1: ICD RJ-11 Style Connector Interface FIGURE 30-2: PICkit™ Programmer Style Connector Interface FIGURE 30-3: Typical Connection for ICSP™ Programming 31.0 Instruction Set Summary 31.1 Read-Modify-Write Operations TABLE 31-1: Opcode Field Descriptions TABLE 31-2: Abbreviation Descriptions FIGURE 31-1: General Format for Instructions TABLE 31-3: PIC16(L)F1704/8 Instruction Set TABLE 31-3: PIC16(L)F1704/8 Instruction Set (Continued) 31.2 Instruction Descriptions 32.0 Electrical Specifications 32.1 Absolute Maximum Ratings(†) 32.2 Standard Operating Conditions FIGURE 32-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F1704/8 Only FIGURE 32-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF1704/8 Only 32.3 DC Characteristics TABLE 32-1: Supply Voltage FIGURE 32-3: POR and POR Rearm with Slow Rising Vdd TABLE 32-2: Supply Current (Idd)(1,2) TABLE 32-3: Power-Down Currents (Ipd)(1,2) TABLE 32-4: I/O Ports TABLE 32-5: Memory Programming Specifications TABLE 32-6: Thermal Characteristics 32.4 AC Characteristics FIGURE 32-4: Load Conditions FIGURE 32-5: Clock Timing TABLE 32-7: Clock Oscillator Timing Requirements TABLE 32-8: Oscillator Parameters FIGURE 32-6: HFINTOSC and MFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 32-9: PLL Clock Timing Specifications FIGURE 32-7: CLKOUT and I/O Timing TABLE 32-10: CLKOUT and I/O Timing Parameters FIGURE 32-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 32-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters FIGURE 32-9: Timer0 and Timer1 External Clock Timings FIGURE 32-10: Brown-Out Reset Timing and Characteristics TABLE 32-12: Timer0 and Timer1 External Clock Requirements FIGURE 32-11: Capture/Compare/PWM Timings (CCP) TABLE 32-13: Capture/Compare/PWM Requirements (CCP) FIGURE 32-12: CLC Propagation Timing TABLE 32-14: Configuration Logic Cell (CLC) Characteristics TABLE 32-15: Analog-to-Digital Converter (ADC) Characteristics(1,2): TABLE 32-16: ADC Conversion Requirements FIGURE 32-13: ADC Conversion Timing (ADC Clock Fosc-based) FIGURE 32-14: ADC Conversion Timing (ADC Clock from FRC) TABLE 32-17: Operational Amplifier (OPA) TABLE 32-18: Comparator Specifications TABLE 32-19: Digital-to-Analog Converter (DAC) Specifications TABLE 32-20: Zero-Cross Pin Specifications FIGURE 32-15: USART Synchronous Transmission (Master/Slave) Timing TABLE 32-21: USART Synchronous Transmission Requirements FIGURE 32-16: USART Synchronous Receive (Master/Slave) Timing TABLE 32-22: USART Synchronous Receive Requirements FIGURE 32-17: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 32-18: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 32-19: SPI Slave Mode Timing (CKE = 0) FIGURE 32-20: SPI Slave Mode Timing (CKE = 1) TABLE 32-23: SPI Mode requirements FIGURE 32-21: I2C Bus Start/Stop Bits Timing TABLE 32-24: I2C Bus Start/Stop Bits Requirements FIGURE 32-22: I2C Bus Data Timing TABLE 32-25: I2C Bus Data Requirements 33.0 DC and AC Characteristics Graphs and Charts 34.0 Development Support 34.1 MPLAB X Integrated Development Environment Software 34.2 MPLAB XC Compilers 34.3 MPASM Assembler 34.4 MPLINK Object Linker/ MPLIB Object Librarian 34.5 MPLAB Assembler, Linker and Librarian for Various Device Families 34.6 MPLAB X SIM Software Simulator 34.7 MPLAB REAL ICE In-Circuit Emulator System 34.8 MPLAB ICD 3 In-Circuit Debugger System 34.9 PICkit 3 In-Circuit Debugger/ Programmer 34.10 MPLAB PM3 Device Programmer 34.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 34.12 Third-Party Development Tools 35.0 Packaging Information 35.1 Package Marking Information Package Marking Information (Continued) Package Marking Information (Continued) 35.2 Package Details Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales