Datasheet MCP606, MCP607, MCP608 (Microchip) - 8

MCP606/7/8/9 Note:
Unless otherwise indicated, V ≈ DD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
500 120 ) VDD = 5.5V VDD =2.5V 100 400 VDD = 5.5V 80 TA = +85°C age (µV) age (µV lt 300 lt T o o 60 A = +25°C V V TA = -40°C et 200 40 fset s 20 Off 100 0 Input Of Representative Part Input 0 -20 0 5 0 5 0 5 0 5 0 5 0 -50 -25 0 25 50 75 100 .5 -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Input Offset Voltage vs. Ambient Temperature. Common Mode Input Voltage.
120 90 160 80 RL = 25 kΩ 100 45 ) 140 GBWP 70 120 60 °) 80 0 Phase Margin Gain 100 50 60 -45 rgin ( a Phase Hz) 80 40 40 -90 (k 60 30 e M as 20 -135 40 20 h P Open-Loop Gain (dB) 0 -180 Open-Loop Phase (° 20 Gain Bandwidth Product 10 VDD = 5.0V -20 -225 0 0 0.01 0.1 1 10 100 1k 10k 100k 1M -50 -25 0 25 50 75 100 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-8:
Open-Loop Gain and Phase
FIGURE 2-11:
Gain Bandwidth Product, vs. Frequency. Phase Margin vs. Ambient Temperature.
140 1000 130 ) B 120 (d age Density Hz) Channel n lt
√
o o 110 100 ratio a (nV/ p 100 Se Channel t 90 Referred to Input Input Noise V 10 80 1.E- 0. 0 1 1 1.E+ 1 00 1.E+ 1 0 0 1 1.E+02 100 1.E+03 1k 1.E+ 10 04 k 1.E+05 100k 1.E+0 100 2 1.E+ 1k03 1.E+04 10k 1.E+05 100k Frequency (Hz) Frequency (Hz) FIGURE 2-9:
Channel-to-Channel
FIGURE 2-12:
Input Noise Voltage Density Separation (MCP607 and MCP609 only). vs. Frequency. DS11177F-page 8 © 2009 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP608. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage at VDD = 5.5V. FIGURE 2-2: Input Offset Voltage at VDD = 2.5V. FIGURE 2-3: Quiescent Current vs. Power Supply Voltage. FIGURE 2-4: Input Offset Voltage Drift Magnitude at VDD = 5.5V. FIGURE 2-5: Input Offset Voltage Drift Magnitude at VDD = 2.5V. FIGURE 2-6: Quiescent Current vs. Ambient Temperature. FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. FIGURE 2-8: Open-Loop Gain and Phase vs. Frequency. FIGURE 2-9: Channel-to-Channel Separation (MCP607 and MCP609 only). FIGURE 2-10: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-11: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-15: CMRR, PSRR vs. Frequency. FIGURE 2-16: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-19: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-20: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-21: Slew Rate vs. Ambient Temperature. FIGURE 2-22: Output Voltage Headroom vs. Ambient Temperature at RL = 5 kW. FIGURE 2-23: The MCP606/7/8/9 Show No Phase Reversal. FIGURE 2-24: Output Short Circuit Current Magnitude vs. Ambient Temperature. FIGURE 2-25: Large-signal, Non-inverting Pulse Response. FIGURE 2-26: Small-signal, Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) Hysteresis (MCP608 only). FIGURE 2-28: Large-signal, Inverting Pulse Response. FIGURE 2-29: Small-signal, Inverting Pulse Response. FIGURE 2-30: Amplifier Output Response Times vs. Chip Select (CS) Pulse (MCP608 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 MCP608 Chip Select 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.8 Application Circuits FIGURE 4-8: Low Side Battery Current Sensor. FIGURE 4-9: Photodiode (in Photo-voltaic mode) and Transimpedance Amplifier. FIGURE 4-10: Photodiode (in Photo- conductive mode) and Transimpedance Amplifier. FIGURE 4-11: Two Op Amp Instrumentation Amplifier. FIGURE 4-12: Three Op Amp Instrumentation Amplifier. FIGURE 4-13: Precision Gain with Good Load Isolation. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information