Datasheet LTC1693 (Linear Technology) - 8

LTC1693
U U W U APPLICATIONS INFORMATION Overview
V + VCC The LTC1693 single and dual drivers allow 3V- or 5V-based LEQ digital circuits to drive power MOSFETs at high speeds. A (LOAD INDUCTOR OR STRAY LEAD power MOSFET’s gate-charge loss increases with switch- INDUCTANCE) ing frequency and transition time. The LTC1693 is capable VDRAIN LTC1693 of driving a 1nF load with a 16ns rise and fall time using a CGD P1 OUT V POWER CC of 12V. This eliminates the need for higher voltage MOSFET supplies, such as 18V, to reduce the gate charge losses. N1 CGS The LTC1693’s 360µA quiescent current is an order of GND magnitude lower than most other drivers/buffers. This 1693 F01 improves system efficiency in both standby and switching operation. Since a power MOSFET generally accounts for
Figure 1. Capacitance Seen by OUT During Switching
the majority of power loss in a converter, addition of the The LTC1693’s output peak currents are 1.4A (P1) and LT1693 to a high power converter design greatly improves 1.7A (N1) respectively. The N-channel MOSFET (N1) has efficiency, using very little board space. higher current drive capability so it can discharge the The LTC1693-1 and LTC1693-2 are dual drivers that are power MOSFET’s gate capacitance during high-to-low electrically isolated. Each driver has independent opera- signal transitions. When the power MOSFET’s gate is tion from the other. Drivers may be used in different parts pulled low by the LTC1693, its drain voltage is pulled high of a system, such as a circuit requiring a floating driver and by its load (e.g., a resistor or inductor). The slew rate of the the second driver being powered with respect to ground. drain voltage causes current to flow back to the MOSFETs gate through its gate-to-drain capacitance. If the MOSFET
Input Stage
driver does not have sufficient sink current capability (low The LTC1693 employs 3V CMOS compatible input thresh- output impedance), the current through the power olds that allow a low voltage digital signal to drive standard MOSFET’s Miller capacitance (CGD) can momentarily pull power MOSFETs. The LTC1693 incorporates a 4V internal the gate high, turning the MOSFET back on. regulator to bias the input buffer. This allows the 3V CMOS
Rise/Fall Time
compatible input thresholds (VIH = 2.6V, VIL = 1.4V) to be independent of variations in VCC. The 1.2V hysteresis Since the power MOSFET generally accounts for the ma- between VIH and VIL eliminates false triggering due to jority of power lost in a converter, it’s important to quickly ground noise during switching transitions. The LTC1693’s turn it either fully “on” or “off” thereby minimizing the tran- input buffer has a high input impedance and draws less sition time in its linear region. The LTC1693 has rise and than 10µA during standby. fall times on the order of 16ns, delivering about 1.4A to 1.7A of peak current to a 1nF load with a VCC of only 12V.
Output Stage
The LTC1693’s rise and fall times are determined by the The LTC1693’s output stage is essentially a CMOS in- peak current capabilities of P1 and N1. The predriver, verter, as shown by the P- and N-channel MOSFETs in shown in Figure 1 driving P1 and N1, uses an adaptive Figure 1 (P1 and N1). The CMOS inverter swings rail-to- method to minimize cross-conduction currents. This is rail, giving maximum voltage drive to the load. This large done with a 6ns nonoverlapping transition time. N1 is fully voltage swing is important in driving external power turned off before P1 is turned-on and vice-versa using this MOSFETs, whose RDS(ON) is inversely proportional to its 6ns buffer time. This minimizes any cross-conduction gate overdrive voltage (VGS – VT). currents while N1 and P1 are switching on and off yet is short enough to not prolong their rise and fall times. 8