Datasheet LTC6903, LTC6904 (Analog Devices) - 9

LTC6903/LTC6904
applicaTions inForMaTion Power-Up State Power Supply Bypass
When power is first applied to the LTC6903/LTC6904, In order to obtain the accuracies represented in this data all register values are automatically reset to 0. This results sheet, it is necessary to provide excellent bypass on the in an output frequency of 1.039kHz with both outputs active. power supply. Adequate bypass is a 1µF capacitor in parallel with a 0.01µF capacitor connected within a few
Output Spectrum
millimeters of the power supply leads. In most frequency ranges, the output of the LTC6903/ LTC6904 is generated as a division of the higher internal
Monotonicity and Linearity
clock frequency. This helps to minimize jitter and sub- The DAC in the LTC6903/LTC6904 is guaranteed to be harmonics at the output of the device. In the highest 10-bit monotonic. Nonlinearity of the DAC is less than 1%. frequency ranges, the division ratio is reduced, which Additionally, the LTC6903/LTC6904 is guaranteed to be will result in greater cycle-to-cycle jitter as well as spurs monotonic when switching between octaves with the at the internal sampling frequency. Because the internal OCT setting bits. For example, the frequency output with control loop runs at 1MHz to 2MHz without regard to the a DAC setting of “1111111111” and an OCT setting of output frequency, output spurs separated from the set “1100” will always be lower than the frequency output frequency by 1MHz to 2MHz may be observed. These with a DAC setting of “0000000000” and an OCT setting spurs are characteristically more than 30dB below the of “1101”. Linearity at these transition points is typically level of the set frequency. around 3 LSBs.
Frequency Settling Output Loading and Accuracy
When frequency settings change, the settling time and Improper loading of the outputs of the LTC6903/LTC6904, shape differ depending on which bits are changed. Changing especially with poor power supply bypassing, will result in only the OCT bits will result in an instantaneous change accuracy problems. At low frequencies, capacitive loading in frequency for OCT values below 10. Values of 10 and of the output is not a concern. At frequencies above 1MHz, above may take up to 100µs to settle due to the action of attention should be paid to minimize the capacitive load internal power conservation circuitry. on the CLK and CLK pins. Changing the DAC bits will result in a smooth transition The LTC6903/LTC6904 is designed to drive up to 5pF between the frequencies, occupying at most 100µs, with on each output with no degradation in accuracy. 5pF is little overshoot. equivalent to one to two HC series logic inputs. A standard Changing both the OCT and DAC bits simultaneously may 10x oscilloscope probe usually presents between 10pF result in considerable excursion beyond the frequencies and 15pF of capacitive load. requested before settling. It is strongly suggested that a high speed buffer is used It should be noted that changing the DAC bits at the lower when driving more than one or two logic inputs, when frequency ranges will result in a seemingly instantaneous driving a line more than 5 centimeters in length, or a frequency change because the settling time depends on capacitive load greater than 5pF. the internal loop frequency rather than the set frequency. 69034fe 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Power Requirements Serial Port Electrical Characteristics Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Theory of Operation Applications Information Package Description Revision History Typical Application Related Parts