Datasheet AD8314 (Analog Devices) - 9
Fabricante | Analog Devices |
Descripción | RF Detector / Controller, 100 MHz TO 2.7 GHz, 45 dB |
Páginas / Página | 21 / 9 — AD8314. AVERAGE: 128 SAMPLES. DN 500mV/VERTICAL. DN 1V/VERTICAL. … |
Revisión | C |
Formato / tamaño de archivo | PDF / 440 Kb |
Idioma del documento | Inglés |
AD8314. AVERAGE: 128 SAMPLES. DN 500mV/VERTICAL. DN 1V/VERTICAL. DIVISION. VUP 500mV/. VERTICAL. DN GND. GND. 1µs PER. HORIZONTAL. PULSED RF
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AD8314 AVERAGE: 128 SAMPLES AVERAGE: 128 SAMPLES V V DN 500mV/VERTICAL DN 1V/VERTICAL DIVISION DIVISION VUP 500mV/ V VERTICAL DN GND DIVISION GND 1µs PER HORIZONTAL DIVISION PULSED RF 0.1GHz, –13dBV VUP 500mV/VERTICAL DIVISION RF INPUT GND 100ns PER 200mV PER HORIZONTAL VUP GND VENBL VERTICAL DIVISION
19 6
DIVISION
0 6-
5V PER VERTICAL DIVISION
01 6- 08
VENBL GND
08 01 01 Figure 16. ENBL Response Time Figure 19. VUP and VDN Response Time, −40 dBm to 0 dBm
TRIG HP8648B 10MHz REF OUTPUT EXT TRIG HP8116A OUT HP8648B 10MHz REF OUTPUT EXT TRIG TRIG SIGNAL PULSE SIGNAL PICOSECOND OUT GENERATOR GENERATOR GENERATOR PULSE LABS PULSE PULSE MODE IN OUT PULSE MODULATION GENERATOR –33dBV RF OUT PULSE OUT MODE RF OUT 3.0V –3dB RF TEK P6204 0.1µF SPLITTER FET PROBE 1 RFIN VPOS 8 3.0V TRIG –3dB 0.1µF 52.3Ω TEK P6204 1 RFIN VPOS 8 2 ENBL V_DN 7 FET PROBE TEK TRIG AD8314 TDS784C 52.3Ω TEK P6204 TEK P6204 SCOPE 3.0V 2 ENBL V_DN 7 3 VSET V_UP 6 FET PROBE TEK FET PROBE AD8314 TDS784C TEK P6204 SCOPE 3 VSET V_UP 6 NC 4 FLTR COMM 5 FET PROBE
17 0 6-
NC 4 FLTR COMM 5 NC = NO CONNECT
08 0 01 02 6-
NC = NO CONNECT
08 01 Figure 17. Test Setup for ENBL Response Time Figure 20. Text Setup for Pulse Response
80 0 10 75 –10 RF INPUT 70 –20 –70dBm ) 65 –30 √Hz 60 –40 55 –50 (µV/ –50dBm ) Y –60dBm B) 50 –60 IT 40 – dBm S (d 45 –70 rees E N eg E 40 –80 UD D D L 1 IT ( 35 –90 –20dBm L E A P 30 –100 R T –30dBm AM HAS 25 –110 P PEC 20 –120 15 –130 ISE S 10 –140 O N 5 –150 0 –160 –5 –170 0.1
8 1
10 100 1k 10k 100k 1M 10M
01
100 1k 10k 100k 1M 10M
02 6- 6-
FREQUENCY (Hz)
08
FREQUENCY (Hz)
08 01 01 Figure 18. AC Response from VSET to V_DN Figure 21. VDN Noise Spectral Density Rev. B | Page 8 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INVERTED OUTPUT APPLICATIONS BASIC CONNECTIONS TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT dBV VS. dBm FILTER CAPACITOR OPERATING IN CONTROLLER MODE POWER-ON AND ENABLE GLITCH INPUT COUPLING OPTIONS INCREASING THE LOGARITHMIC SLOPE IN MEASUREMENT MODE EFFECT OF WAVEFORM TYPE ON INTERCEPT MOBILE HANDSET POWER CONTROL EXAMPLES OPERATION AT 2.7 GHz USING THE LFCSP PACKAGE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE