Datasheet ADL5902 (Analog Devices) - 7

ADL5902 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
TEMPERATURE REFERENCE TEMP (Pin 8) Output Voltage TA = 25°C, RL ≥ 10 kΩ 1.4 V Temperature Coefficient −40°C ≤ TA ≤ +125°C, RL ≥ 10 kΩ 4.9 mV/°C Short-Circuit Current Source/ Sink 25°C ≤ TA ≤ 125°C 4/0.05 mA Capability −40°C ≤ TA < +25°C 3/0.05 mA Voltage Regulation TA = 25°C, ILOAD = 1 mA −2.8 % RMS TARGET INTERFACE VTGT (Pin 12) Input Voltage Range 0.2 2.5 V Input Bias Current VTGT = 0.8 V 8 μA Input Resistance 100 kΩ POWER-DOWN INTERFACE Pin TADJ/PWDN (Pin 1) Voltage Level to Enable VPWDN decreasing 4 V Voltage Level to Disable VPWDN increasing 4.9 V Input Current VPWDN = 5 V 1 μA VPWDN = 4.5 V 500 μA VPWDN = 0 V 3 μA Enable Time VTADJ low to VOUT at 1 dB of final value, 5 μs CLPA/B = 220 pF, PIN = 0 dBm Disable Time VTADJ high to VOUT at 1 dB of final value, 3 μs CLPA/B = 220 pF, PIN = 0 dBm POWER SUPPLY INTERFACE VPOS (Pin 3, Pin 10) Supply Voltage 4.5 5 5.5 V Quiescent Current TA = 25°C, PIN < −60 dBm 73 mA TA = 125°C, PIN < −60 dBm 90 mA Power-Down Current VTADJ > VS − 0.1 V 300 μA Rev. B | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE BASIS FOR ERROR CALCULATIONS MEASUREMENT MODE BASIC CONNECTIONS SETTING VTADJ SETTING VTGT CHOOSING A VALUE FOR CLPF OUTPUT VOLTAGE SCALING SYSTEM CALIBRATION AND ERROR CALCULATION HIGH FREQUENCY PERFORMANCE LOW FREQUENCY PERFORMANCE DESCRIPTION OF CHARACTERIZATION EVALUATION BOARD SCHEMATICS AND ARTWORK ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE