Datasheet ADL5903 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 200 MHz to 6 GHz 35 dB TruPwr™ Detector |
| Páginas / Página | 22 / 9 — Data Sheet. ADL5903. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. RFIN 1. … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 1.5 Mb |
| Idioma del documento | Inglés |
Data Sheet. ADL5903. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. RFIN 1. 8 NIC. GND 2. 7 VRMS. TOP VIEW. CRMS 3. 6 ENBL. (Not to Scale)
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Data Sheet ADL5903 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 1 8 NIC GND 2 7 VRMS ADL5903 TOP VIEW CRMS 3 6 ENBL (Not to Scale) CREG 4 5 VPOS NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GND AND REQUIRES A GOOD THERMAL AND ELECTRICAL
002 9-
CONNECTION TO THE GROUND OF THE PRINTED CIRCUIT BOARD (PCB).
1176 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 RFIN Signal Input. This pin is internally ac-coupled with a broadband matching network. See the RF Input Interface section for broadband matching options. 2 GND Device Ground. Connect GND to system ground using a low impedance path. 3 CRMS RMS Averaging Pin. Connect a capacitor between the CREG and CRMS pins for rms averaging. See the Choosing a Value for CRMS section for choosing the correct CRMS capacitor value. 4 CREG Bypass Capacitor Connection for On-Chip Regulator. Bypass this pin to ground using a capacitor and a series resistor. See Basic Connections section for more information. 5 VPOS Supply Voltage. The operational range is 3.0 V to 5.25 V. 6 ENBL Enable. Connect the ENBL pin to a logic high (2 V to VPOS) to enable the device. Connect the ENBL pin to a logic low (0 V to 0.6 V) to disable the device. 7 VRMS Signal Output. The output from the VRMS pin is proportional to the logarithm of the rms value at the input level. 8 NIC No Internal Connection. Do not connect to this pin. This pin is not internally connected. 0 EP Exposed Pad. The exposed pad is internally connected to GND and requires a good thermal and electrical connection to the ground of the printed circuit board (PCB). Rev. B | Page 7 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS MEASUREMENT SETUPS THEORY OF OPERATION RF INPUT INTERFACE BASIC CONNECTIONS CHOOSING A VALUE FOR CRMS DEVICE CALIBRATION AND ERROR CALCULATION EVALUATION BOARD SCHEMATIC AND CONFIGURATION OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADL5903 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 1 8 NIC GND 2 7 VRMS ADL5903 TOP VIEW CRMS 3 6 ENBL (Not to Scale) CREG 4 5 VPOS NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GND AND REQUIRES A GOOD THERMAL AND ELECTRICAL
002 9-
CONNECTION TO THE GROUND OF THE PRINTED CIRCUIT BOARD (PCB).
1176 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 RFIN Signal Input. This pin is internally ac-coupled with a broadband matching network. See the RF Input Interface section for broadband matching options. 2 GND Device Ground. Connect GND to system ground using a low impedance path. 3 CRMS RMS Averaging Pin. Connect a capacitor between the CREG and CRMS pins for rms averaging. See the Choosing a Value for CRMS section for choosing the correct CRMS capacitor value. 4 CREG Bypass Capacitor Connection for On-Chip Regulator. Bypass this pin to ground using a capacitor and a series resistor. See Basic Connections section for more information. 5 VPOS Supply Voltage. The operational range is 3.0 V to 5.25 V. 6 ENBL Enable. Connect the ENBL pin to a logic high (2 V to VPOS) to enable the device. Connect the ENBL pin to a logic low (0 V to 0.6 V) to disable the device. 7 VRMS Signal Output. The output from the VRMS pin is proportional to the logarithm of the rms value at the input level. 8 NIC No Internal Connection. Do not connect to this pin. This pin is not internally connected. 0 EP Exposed Pad. The exposed pad is internally connected to GND and requires a good thermal and electrical connection to the ground of the printed circuit board (PCB). Rev. B | Page 7 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS MEASUREMENT SETUPS THEORY OF OPERATION RF INPUT INTERFACE BASIC CONNECTIONS CHOOSING A VALUE FOR CRMS DEVICE CALIBRATION AND ERROR CALCULATION EVALUATION BOARD SCHEMATIC AND CONFIGURATION OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE