Datasheet AD8556 (Analog Devices) - 8

Data Sheet AD8556 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 8 VSS FILT/DIGOUT AD8556 2 7 VOUT TOP VIEW DIGIN 3 6 VCLAMP (Not to Scale)
002
VNEG 4 5 VPOS
05448- Figure 2. 8-Lead SOIC_N Pin Configuration
Table 4. 8-Lead SOIC_N Pin Function Descriptions SOIC_N Mnemonic Description
1 VDD Positive Supply Voltage. 2 FILT/DIGOUT Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output. 3 DIGIN Digital Input. 4 VNEG Negative Amplifier Input (Inverting Input). 5 VPOS Positive Amplifier Input (Noninverting Input). 6 VCLAMP Set Clamp Voltage at Output. 7 VOUT Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output. 8 VSS Negative Supply Voltage. Rev. B | Page 7 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Parity Error Detection Read Mode Sense Current Programming Procedure Determining Optimal Gain and Offset Codes EMI/RFI PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE