Datasheet AD8251 (Analog Devices) - 9

AD8251 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted.
2700 800 2400 700 2100 S 600 S T T 1800 UNI 500 UNI F F 1500 R O R O 400 1200 BE BE M 300 NU NUM 900 200 600
6
100
9 00
300
00 7- 7- 28 28
0
06
0
06
–30 –20 –10 0 10 20 30 –120 –90 –60 –30 0 30 60 90 120 INPUT OFFSET CURRENT (nA) CMRR (µV/V)
Figure 6. Typical Distribution of CMRR, G = 1 Figure 9. Typical Distribution of Input Offset Current
90 500 80 70 400 S T ) 60 UNI √Hz F 300 V/ 50 n R O G = 1 E ( BE IS 40 O 200 N NUM 30 G = 2 G = 4 20 100 G = 8
07 0 10
10
0 7- 7- 28 28
0
06 06
0 –200 –100 0 100 200 1 10 100 1k 10k 100k INPUT OFFSET VOLTAGE, VOSI , RTI (µV) FREQUENCY (Hz)
Figure 7. Typical Distribution of Offset Voltage, VOSI Figure 10. Voltage Spectral Density Noise vs. Frequency
800 S T 600 UNI F R O BE 400 M NU 200
8 00 7- 1
2µV/DIV 1s/DIV
28 -01
0
06 87 62
–30 –20 –10 0 10 20 30
0
INPUT BIAS CURRENT (nA)
Figure 8. Typical Distribution of Input Bias Current Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Rev. B | Page 8 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE