ADA4939-1/ADA4939-2Data Sheet33VV2OUT, dm = 100mV p-p2OUT, dm = 2V p-pB)1B)d1dN (0N (0AI–1AI–1GGP–2PO–2OO–3O–3-L-LD–4DE–4ES–5SO–5O–6–6D CLD CLE–7E–7IZIZ–8–8ALAL–9–9RMRM–10–10NORNOR–11L = 1kΩ–11L = 1kΩRL = 200ΩRL = 200Ω–12–121101001k 13 16 0 1101001k 0 9- 9- FREQUENCY (MHz) 42 FREQUENCY (MHz) 42 07 07 Figure 13. Small Signal Frequency Response for Various Loads Figure 16. Large Signal Frequency Response for Various Loads 6 V–55OUT, dm = 100mV p-pVOUT, dm = 2V p-p–60HD2, G = 23–65HD3, G = 2Bc)–70dHD2, G = 3.16)(HD3, G = 3.16BN–750HD2, G = 5(dIO TINR–80HD3, G = 5OGAT–85SM–3DIOC–90VIC N O–95–6–100ARM HVOCM = 1.0V–105VOCM = 3.9VV–110OCM = 2.5V–91101001k 19 –115 0 9- 110100 22 0 FREQUENCY (MHz) 42 9- 07 FREQUENCY (MHz) 42 07 Figure 14. VOCM Small Signal Frequency Response at Various DC Levels Figure 17. Harmonic Distortion vs. Frequency at Various Gains 0.5–60VOUT, dm = 100mV p-pVOUT, dm = 2V p-p0.4VB)–65S = ±2.5VdHD2, RL, dm = 1kΩN (0.3–70HD3, RAIBc)L, dm = 1kΩHD2, RGdL, dm = 200Ω0.2(P–75NHD3, RL, dm = 200ΩO OIO0.1–80-LRTDOE0TS–85SO–0.1C DI–90D CLNIERL = 1kΩOIZ –0.2RM–95L = 200ΩAL –0.3RL = 1kΩ OUT1HAR –100RMRL = 1kΩ OUT2NO –0.4RL = 200Ω OUT1–105RL = 200Ω OUT2–0.5–1101101001k 20 23 0 110100 0 9- 9- FREQUENCY (MHz) 42 FREQUENCY (MHz) 42 07 07 Figure 15. 0.1 dB Flatness Small Signal Response for Various Loads Figure 18. Harmonic Distortion vs. Frequency at Various Loads Rev. A | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 5 V OPERATION ±DIN to VOUT, dm Performance VOCM to VOUT, cm Performance General Performance 3.3 V OPERATION ±DIN to VOUT, dm Performance VOCM to VOUT, cm Performance General Performance ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OPERATIONAL DESCRIPTION DEFINITION OF TERMS Differential Voltage Common-Mode Voltage Balance THEORY OF OPERATION ANALYZING AN APPLICATION CIRCUIT SETTING THE CLOSED-LOOP GAIN STABLE FOR GAINS ≥2 ESTIMATING THE OUTPUT NOISE VOLTAGE IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT Terminating a Single-Ended Input INPUT COMMON-MODE VOLTAGE RANGE INPUT AND OUTPUT CAPACITIVE AC COUPLING MINIMUM RG VALUE OF 50 Ω SETTING THE OUTPUT COMMON-MODE VOLTAGE LAYOUT, GROUNDING, AND BYPASSING HIGH PERFORMANCE ADC DRIVING OUTLINE DIMENSIONS ORDERING GUIDE