Datasheet ADL5205 (Analog Devices) - 8

Data Sheet ADL5205 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 0 A A / / A A _ _ K T L A 2 C D A A/ _ _ A H P A N N A C U _ D D T M C A P P A INA– INA+ W C N F U U L V V P V PIN 1 DNC D INDICATOR 0 9 8 7 6 5 4 3 1 4 2 3 3 3 3 3 3 3 3 3 CSA/A3 1 30 VOUTA– A4 2 29 VOUTA+ A5 3 28 DNC MODE1 4 27 VPOS ADL5205 MODE0 5 26 DNC PM 6 TOP VIEW 25 DNC DNC 7 (Not to Scale) 24 VPOS SDIO/B5 8 23 DNC SCLK/B4 9 22 VOUTB+ GS1/CSB/B3 10 21 VOUTB– 11 21 31 4 51 6 7 1 1 81 91 0 1 2 2 1 0 – + B B B B / B/ B/ H B B P M B C N N U DNC DNC _ B_ B_ C T VI VI V A K T W A F P / L A L 0 C D S _ _ G N N D D P P U U NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS. 2. THE EXPOSED PAD MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PLANE. THIS IS
5
THE GROUND (0V) REFERENCE FOR ALL THE
-00
VOLTAGES IN TABLE 1.
488 13 Figure 5. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 CSA/A3 Channel A Select in Serial Mode (CSA). When serial mode is enabled, a logic low selects Channel A. Bit 3 for Channel A in Parallel Gain Control Interface Mode (A3). 2 A4 Bit 4 for Channel A in Parallel Gain Control Interface Mode (A4). 3 A5 Bit 5 for Channel A in Parallel Gain Control Interface Mode (A5). 4 MODE1 MSB for Mode Control. Use both the MODE0 and MODE1 pins to select parallel, SPI, or up/down interface mode. 5 MODE0 LSB for Mode Control. Use both the MODE1 and MODE0 pins to select parallel, SPI, or up/down interface mode. 6 PM Power Mode. Set this pin to logic low to enable high performance mode, or logic high to enable low power mode. 7, 19, 20, 23, 25, 26, DNC Do Not Connect. Do not connect to these pins. 28, 31, 32 8 SDIO/B5 Serial Data Input and Output in SPI Mode (SDIO). Bit 5 for Channel B in Parallel Gain Control Interface Mode (B5). 9 SCLK/B4 Serial Clock Input in SPI Mode (SCLK). Bit 4 for Channel B in Parallel Gain Control Interface (B4). 10 GS1/CSB/B3 MSB for the Gain Step Size Control in Up/Down Mode (GS1). Channel B Select in Serial Mode (CSB). When serial mode is enabled, a logic low selects Channel B. Bit 3 for Channel B in Parallel Gain Control Mode (B3). 11 GS0/FA_B/B2 LSB for the Gain Step Size Control in Up/Down Mode (GS0). Fast Attack for Channel B (FA_B). In serial mode, a logic high on this pin attenuates Channel B according to the FA bit values in the control register. Bit 2 for Channel B in Parallel Gain Control Interface (B2). 12 UPDN_CLK_B/B1 Clock Interface for the Channel B Up/Down Function (UPDN_CLK_B). Bit 1 for Channel B in Parallel Gain Control Interface Mode (B1). 13 UPDN_DAT_B/B0 Data Pin for the Channel B Up/Down Function (UPDN_DAT_B). Bit 0 for Channel B in Parallel Gain Control Interface Mode (B0). Rev. 0 | Page 7 of 31 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE JUNCTION TO BOARD THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE CONTROL/LOGIC CIRCUITRY COMMON-MODE VOLTAGE APPLICATIONS INFORMATION BASIC CONNECTIONS DIGITAL INTERFACE OVERVIEW Parallel Digital Interface Serial Peripheral Interface (SPI) Up/Down Interface SPI READ ADC INTERFACING NOISE FIGURE vs. GAIN SETTING EVALUATION BOARD OVERVIEW POWER SUPPLY INTERFACE SIGNAL INPUTS AND OUTPUTS MANUAL CONTROLS Mode Switches Channel Control Switches PARALLEL INTERFACE SERIAL INTERFACE STANDARD DEVELOPMENT PLATFORM (SDP) INTERFACE EVALUATION BOARD CONTROL SOFTWARE COMMAND LINE CONTROL PROGRAM GRAPHICAL USER INTERFACE (GUI) PROGRAM EVALUATION BOARD SCHEMATICS AND LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE